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git01.mediatek.com / filogic / uboot / 1f6668a9b81851807939ef970fc352ca204b7a44 / arch / arm / dts / stm32mp15xx-dhcom-u-boot.dtsi
  1. 6d39705 arm: dts: stm32mp15: alignment with v5.11-rc2 by Patrick Delaunay · Mon Jan 11 12:33:36 2021 +0100
  2. ccfcde3 ARM: dts: stm32: Switch to MCO2 for PHY 50 MHz clock by Marek Vasut · Tue Dec 01 11:34:48 2020 +0100
  3. b0a2a49 ARM: dts: stm32: Update eth1addr from EEPROM if eth1 present by Marek Vasut · Fri Jul 31 01:34:50 2020 +0200
  4. 4958e14 Revert "ARM: dts: stm32: Reinstate card detect behavior on DHSOM" by Patrick Delaunay · Tue Jul 07 18:46:08 2020 +0200
  5. 72b1080 ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPL by Patrick Delaunay · Mon May 25 12:19:48 2020 +0200
  6. bee4b5d ARM: dts: stm32: Reinstate card detect behavior on DHSOM by Marek Vasut · Thu Jun 18 20:35:17 2020 +0200
  7. 8759f3f ARM: stm32: Hog GPIO PF7 high on DHCOM to unlock SPI NOR nWP by Marek Vasut · Mon Apr 27 12:26:43 2020 +0200
  8. 272198e ARM: dts: stm32: Synchronize DDR setttings on DH SoMs by Marek Vasut · Wed Apr 29 15:08:38 2020 +0200
  9. 39221b5 ARM: stm32: Implement DDR3 coding on DHCOR SoM by Marek Vasut · Wed Apr 22 13:18:14 2020 +0200
  10. 47b98ba ARM: stm32: Implement board coding on AV96 by Marek Vasut · Wed Apr 22 13:18:11 2020 +0200
  11. 0839ea9 ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2 by Marek Vasut · Sat Mar 28 02:01:58 2020 +0100
  12. 48c5e90 ARM: dts: stm32mp1: DT alignment with Linux 5.6-rc1 by Patrick Delaunay · Fri Mar 06 17:54:41 2020 +0100
  13. c22caac ARM: dts: stm32m1: add reg for pll nodes by Patrick Delaunay · Tue Jan 28 10:11:03 2020 +0100
  14. 84159e8 ARM: dts: stm32mp1: move FDCAN to PLL4_R by Antonio Borneo · Tue Jan 28 10:11:01 2020 +0100
  15. 5ff0529 ARM: dts: stm32: Add DH Electronics DHCOM SoM and PDK2 board by Marek Vasut · Fri Jan 24 18:39:16 2020 +0100