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git01.mediatek.com / filogic / uboot / 1e34e834b5c4abd5f3776261ef7514a2934a5c06 / board / stx / stxssa / ddr.c
  1. c68e86c powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board by Kumar Gala · 14 years ago
  2. b78c7bf powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() by Kumar Gala · 14 years ago
  3. dd67ddc stx: create common vendor/board hierarchy for STx boards by Alex Dubov · 15 years ago[Renamed from board/stxssa/ddr.c]
  4. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  5. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  6. 0abad32 FSL DDR: Convert STXSSA to new DDR code. by Kumar Gala · 16 years ago