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git01.mediatek.com / filogic / uboot / 1e271e4a5197f6045b630ab5640ae2043f5700a8 / drivers
  1. 1e271e4 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 5 by Marek Vasut · Sat Aug 01 21:24:31 2015 +0200
  2. 71c1a00 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 4 by Marek Vasut · Sat Aug 01 21:21:21 2015 +0200
  3. 3a07911 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 3 by Marek Vasut · Sat Aug 01 21:16:20 2015 +0200
  4. 7697ff7 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 2 by Marek Vasut · Sat Aug 01 20:58:44 2015 +0200
  5. 4fccfa4 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 1 by Marek Vasut · Sat Aug 01 20:39:46 2015 +0200
  6. 4f3adbf ddr: altera: sdram: Introduce socfpga_sdram_config() structure by Marek Vasut · Sat Aug 01 20:30:10 2015 +0200
  7. 92e8e6f ddr: altera: sdram: Clean up set_sdr_mp_threshold() by Marek Vasut · Sat Aug 01 20:14:11 2015 +0200
  8. 44f09cc ddr: altera: sdram: Clean up set_sdr_mp_pacing() by Marek Vasut · Sat Aug 01 20:12:31 2015 +0200
  9. b933b19 ddr: altera: sdram: Clean up set_sdr_mp_weight() by Marek Vasut · Sat Aug 01 20:10:23 2015 +0200
  10. f904a86 ddr: altera: sdram: Clean up set_sdr_fifo_cfg() by Marek Vasut · Sat Aug 01 20:04:33 2015 +0200
  11. 9d64f19 ddr: altera: sdram: Clean up set_sdr_static_cfg() by Marek Vasut · Sat Aug 01 20:04:19 2015 +0200
  12. 820b0d9 ddr: altera: sdram: Clean up set_sdr_addr_rw() by Marek Vasut · Sat Aug 01 19:50:56 2015 +0200
  13. 6e9af9b ddr: altera: sdram: Clean up set_sdr_dram_timing*() by Marek Vasut · Sat Aug 01 19:45:24 2015 +0200
  14. 82a2764 ddr: altera: sdram: Clean up set_sdr_ctrlcfg() by Marek Vasut · Sat Aug 01 19:33:40 2015 +0200
  15. 724c50f ddr: altera: sdram: Clean up compute_errata_rows() part 2 by Marek Vasut · Sat Aug 01 19:20:19 2015 +0200
  16. 186880e ddr: altera: sdram: Clean up compute_errata_rows() part 1 by Marek Vasut · Sat Aug 01 18:54:34 2015 +0200
  17. 2fda506 ddr: altera: sdram: Switch to generic_hweight32() by Marek Vasut · Sat Aug 01 18:46:55 2015 +0200
  18. 98d279a ddr: altera: Clean up of delay_for_n_mem_clocks() part 5 by Marek Vasut · Sun Jul 26 11:46:04 2015 +0200
  19. 7574c87 ddr: altera: Clean up of delay_for_n_mem_clocks() part 4 by Marek Vasut · Sun Jul 26 11:44:54 2015 +0200
  20. 13ee438 ddr: altera: Clean up of delay_for_n_mem_clocks() part 3 by Marek Vasut · Sun Jul 26 11:42:53 2015 +0200
  21. 4b203df ddr: altera: Clean up of delay_for_n_mem_clocks() part 2 by Marek Vasut · Sun Jul 26 11:34:09 2015 +0200
  22. 50d7199 ddr: altera: Clean up of delay_for_n_mem_clocks() part 1 by Marek Vasut · Sun Jul 26 11:11:28 2015 +0200
  23. c140275 ddr: altera: Minor clean up of rw_mgr_mem_handoff() by Marek Vasut · Sun Jul 26 10:59:19 2015 +0200
  24. a358127 ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo() by Marek Vasut · Tue Jul 21 06:18:57 2015 +0200
  25. 2da0257 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end() by Marek Vasut · Sat Jul 18 05:58:44 2015 +0200
  26. adbaa2d ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue() by Marek Vasut · Tue Jul 21 06:00:36 2015 +0200
  27. c67d962 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3 by Marek Vasut · Tue Jul 21 05:57:11 2015 +0200
  28. bc773a1 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2 by Marek Vasut · Tue Jul 21 05:54:39 2015 +0200
  29. 0b97c42 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1 by Marek Vasut · Tue Jul 21 05:43:37 2015 +0200
  30. 2595b24 ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5 by Marek Vasut · Tue Jul 21 05:33:49 2015 +0200
  31. fc2ec8f ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4 by Marek Vasut · Tue Jul 21 05:32:49 2015 +0200
  32. 1bb221e ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3 by Marek Vasut · Tue Jul 21 05:29:05 2015 +0200
  33. 4e79b0a ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2 by Marek Vasut · Tue Jul 21 05:26:58 2015 +0200
  34. affbc89 ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1 by Marek Vasut · Tue Jul 21 05:00:42 2015 +0200
  35. 9cdbb96 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11 by Marek Vasut · Tue Jul 21 04:27:32 2015 +0200
  36. d29f804 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10 by Marek Vasut · Sat Jul 18 20:44:28 2015 +0200
  37. dfed1e6 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9 by Marek Vasut · Sat Jul 18 20:42:27 2015 +0200
  38. b69c247 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8 by Marek Vasut · Sat Jul 18 20:34:00 2015 +0200
  39. f1b8f71 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7 by Marek Vasut · Sat Jul 18 19:57:12 2015 +0200
  40. 89feb50 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6 by Marek Vasut · Sat Jul 18 19:46:26 2015 +0200
  41. aa0e6e1 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5 by Marek Vasut · Sat Jul 18 19:18:06 2015 +0200
  42. ca8ea37 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4 by Marek Vasut · Sat Jul 18 08:01:45 2015 +0200
  43. 85cd4d7 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3 by Marek Vasut · Mon Jul 13 02:48:34 2015 +0200
  44. e624caf ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2 by Marek Vasut · Mon Jul 13 02:38:15 2015 +0200
  45. b20a506 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1 by Marek Vasut · Mon Jul 13 02:11:02 2015 +0200
  46. 4a78cc7 ddr: altera: Clean up rw_mgr_mem_calibrate_writes() by Marek Vasut · Sat Jul 18 07:23:25 2015 +0200
  47. 656002e ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5 by Marek Vasut · Mon Jul 20 03:26:05 2015 +0200
  48. 50a780f ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4 by Marek Vasut · Sun Jul 19 07:57:28 2015 +0200
  49. 28957f3 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3 by Marek Vasut · Sun Jul 19 07:51:17 2015 +0200
  50. c6c1fe7 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2 by Marek Vasut · Sun Jul 19 07:48:58 2015 +0200
  51. a005c77 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1 by Marek Vasut · Sun Jul 19 07:44:21 2015 +0200
  52. a50d5d7 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks() by Marek Vasut · Sun Jul 19 07:35:36 2015 +0200
  53. ec4bbd3 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 7 by Marek Vasut · Mon Jul 20 09:11:09 2015 +0200
  54. 28dbf12 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 6 by Marek Vasut · Mon Jul 20 09:20:42 2015 +0200
  55. 59729a6 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 5 by Marek Vasut · Mon Jul 20 09:20:20 2015 +0200
  56. 6ff36b7 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 4 by Marek Vasut · Sun Jul 19 07:27:06 2015 +0200
  57. deebda8 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3 by Marek Vasut · Sun Jul 19 07:03:15 2015 +0200
  58. 970539d ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2 by Marek Vasut · Sun Jul 19 07:00:26 2015 +0200
  59. 4896bcc ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 1 by Marek Vasut · Sun Jul 19 02:42:21 2015 +0200
  60. 088eb21 ddr: altera: Clean up find_vfifo_read() by Marek Vasut · Sun Jul 19 06:45:43 2015 +0200
  61. 42e43ab ddr: altera: Clean up rw_mgr_*_vfifo() part 2 by Marek Vasut · Sun Jul 19 06:37:51 2015 +0200
  62. 1c9f25b ddr: altera: Clean up rw_mgr_*_vfifo() part 1 by Marek Vasut · Sun Jul 19 06:25:27 2015 +0200
  63. 6394ef5 ddr: altera: Clean up sdr_*_phase() part 10 by Marek Vasut · Sun Jul 19 06:04:00 2015 +0200
  64. 6eff803 ddr: altera: Clean up sdr_*_phase() part 9 by Marek Vasut · Sun Jul 19 05:48:30 2015 +0200
  65. f260eec ddr: altera: Clean up sdr_*_phase() part 8 by Marek Vasut · Sun Jul 19 05:42:43 2015 +0200
  66. 2700b9c ddr: altera: Clean up sdr_*_phase() part 7 by Marek Vasut · Sun Jul 19 05:40:06 2015 +0200
  67. 6da8ae4 ddr: altera: Clean up sdr_*_phase() part 6 by Marek Vasut · Sun Jul 19 05:35:40 2015 +0200
  68. f2b02d4 ddr: altera: Clean up sdr_*_phase() part 5 by Marek Vasut · Sun Jul 19 05:26:49 2015 +0200
  69. b148ebe ddr: altera: Clean up sdr_*_phase() part 4 by Marek Vasut · Sun Jul 19 05:01:12 2015 +0200
  70. 434f639 ddr: altera: Clean up sdr_*_phase() part 3 by Marek Vasut · Sun Jul 19 04:37:08 2015 +0200
  71. 6ff1c85 ddr: altera: Clean up sdr_*_phase() part 2 by Marek Vasut · Sun Jul 19 04:34:12 2015 +0200
  72. 139ad79 ddr: altera: Clean up sdr_*_phase() part 1 by Marek Vasut · Sun Jul 19 04:29:21 2015 +0200
  73. fea03c3 ddr: altera: Clean up sdr_find_window_centre() part 3 by Marek Vasut · Sun Jul 19 04:14:32 2015 +0200
  74. ea4c4bb ddr: altera: Clean up sdr_find_window_centre() part 2 by Marek Vasut · Sun Jul 19 04:04:33 2015 +0200
  75. d996e80 ddr: altera: Clean up sdr_find_window_centre() part 1 by Marek Vasut · Sun Jul 19 02:56:59 2015 +0200
  76. 3aa19dc ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 4 by Marek Vasut · Sat Jul 18 04:28:42 2015 +0200
  77. 1beb243 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 3 by Marek Vasut · Sat Jul 18 04:24:49 2015 +0200
  78. faf820a ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2 by Marek Vasut · Sat Jul 18 04:20:26 2015 +0200
  79. bb9a5f7 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 1 by Marek Vasut · Sat Jul 18 04:16:45 2015 +0200
  80. 55c4d69 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns() by Marek Vasut · Sat Jul 18 03:55:07 2015 +0200
  81. fcef833 ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks() by Marek Vasut · Sat Jul 18 03:36:09 2015 +0200
  82. 6a75278 ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup by Marek Vasut · Sat Jul 18 03:34:22 2015 +0200
  83. 349ea3e ddr: altera: Extract Centering DQ/DQS from rw_mgr_mem_calibrate_vfifo() by Marek Vasut · Sat Jul 18 03:10:31 2015 +0200
  84. feb5e65 ddr: altera: Extract DQS enable calibration from rw_mgr_mem_calibrate_vfifo() by Marek Vasut · Sat Jul 18 02:57:32 2015 +0200
  85. 6ca5b96 ddr: altera: Extract guaranteed write from rw_mgr_mem_calibrate_vfifo() by Marek Vasut · Sat Jul 18 02:46:56 2015 +0200
  86. 912d43e ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7 by Marek Vasut · Sat Jul 18 03:15:34 2015 +0200
  87. e42fcea ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 6 by Marek Vasut · Fri Jul 17 04:24:18 2015 +0200
  88. 0d9f9d5 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 5 by Marek Vasut · Fri Jul 17 03:54:34 2015 +0200
  89. f2a4bda ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 4 by Marek Vasut · Fri Jul 17 03:50:17 2015 +0200
  90. d7f4915 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3 by Marek Vasut · Fri Jul 17 03:44:26 2015 +0200
  91. aff1a5f ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2 by Marek Vasut · Fri Jul 17 03:22:31 2015 +0200
  92. c27ea62 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 1 by Marek Vasut · Fri Jul 17 03:16:45 2015 +0200
  93. 1185e22 ddr: altera: Minor clean up of rw_mgr_mem_initialize() by Marek Vasut · Sun Jul 26 10:57:06 2015 +0200
  94. d9fcf9a ddr: altera: Internal mem_calibrate() cleanup part 6 by Marek Vasut · Mon Jul 20 04:34:51 2015 +0200
  95. 0568f22 ddr: altera: Internal mem_calibrate() cleanup part 5 by Marek Vasut · Fri Jul 17 02:50:56 2015 +0200
  96. fc38d5c ddr: altera: Internal mem_calibrate() cleanup part 4 by Marek Vasut · Fri Jul 17 02:40:21 2015 +0200
  97. 6db5573 ddr: altera: Internal mem_calibrate() cleanup part 3 by Marek Vasut · Fri Jul 17 02:38:51 2015 +0200
  98. f04045f ddr: altera: Internal mem_calibrate() cleanup part 2 by Marek Vasut · Fri Jul 17 02:31:04 2015 +0200
  99. d6f2879 ddr: altera: Internal mem_calibrate() cleanup part 1 by Marek Vasut · Fri Jul 17 02:21:47 2015 +0200
  100. b984ee8 ddr: altera: Trivial mem_calibrate() indent cleanup by Marek Vasut · Fri Jul 17 02:07:12 2015 +0200