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git01.mediatek.com / filogic / uboot / 1cfd5509cb130753af04843b4e88a0c5eb139371 / drivers / clk / rockchip
  1. 1cfd550 rockchip: rk3328: add clock driver by Kever Yang · Thu Feb 23 15:37:52 2017 +0800
  2. 5616c63 rockchip: rk3188: Add clock driver by Heiko Stübner · Sat Feb 18 19:46:34 2017 +0100
  3. 643549b rockchip: clk: rk3288: limit gpll and cpll init to SPL build by Heiko Stübner · Sat Feb 18 19:46:22 2017 +0100
  4. e198053 rockchip: clk: rk3399: update driver for spl by Kever Yang · Mon Feb 13 17:38:56 2017 +0800
  5. cb1c7af rockchip: clk: Support setting ACLK by Simon Glass · Sun Nov 13 14:22:13 2016 -0700
  6. 901c2ce rockchip: rk3288: Move rockchip_get_cru() out of the driver by Simon Glass · Sat Oct 01 20:04:52 2016 -0600
  7. d1dfea7 rockchip: rk3399: Move rockchip_get_cru() out of the driver by Simon Glass · Sat Oct 01 20:04:51 2016 -0600
  8. 3814f0e rockchip: rk3036: Move rockchip_get_cru() out of the driver by Simon Glass · Sat Oct 01 20:04:50 2016 -0600
  9. 78b6c3f clk: rk3399: fix rockchip_get_cru by Jacob Chen · Tue Sep 27 15:48:45 2016 +0800
  10. 4051462 clk: rk3288: add PWM clock get rate by Kever Yang · Fri Aug 12 17:57:05 2016 +0800
  11. e54d26a clk: rk3399: add pmucru controller support by Kever Yang · Fri Aug 12 17:47:15 2016 +0800
  12. 1b7dcc3 rockchip: remove log2 reimplementation from clock drivers by Heiko Stübner · Fri Jul 22 23:51:06 2016 +0200
  13. dc850de clock: rk3399: add support for dwmmc 400K by Kever Yang · Thu Aug 04 11:44:58 2016 +0800
  14. 4776f0b move: rockchip: move clock drivers into a subdirectory by Heiko Stübner · Fri Jul 29 14:47:21 2016 +0200