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git01.mediatek.com / filogic / uboot / 1b7028d44fc3eaabf279e70a13343457851586f9 / drivers / ddr / altera / sdram_arria10.c
  1. 1d91ba7 common: Move some cache and MMU functions out of common.h by Simon Glass · Thu Nov 14 12:57:37 2019 -0700
  2. 0f36715 ddr: socfpga: Clean up ddr_setup() by Marek Vasut · Sat Mar 09 21:58:09 2019 +0100
  3. 569fe4a ddr: socfpga: Clean up EMIF reset by Marek Vasut · Sat Mar 09 21:57:58 2019 +0100
  4. a9c0470 ddr: socfpga: Fix EMIF clear timeout by Marek Vasut · Fri Mar 08 19:11:55 2019 +0100
  5. 6b44050 ddr: socfpga: Fix newline in debug print on A10 by Marek Vasut · Wed Mar 06 17:18:22 2019 +0100
  6. e2bc6b1 ddr: socfpga: Fix IO in Arria10 DDR driver by Marek Vasut · Tue Mar 05 18:37:02 2019 +0100
  7. 3693897 ddr: altera: Add ECC DRAM scrubbing support for Arria10 by Marek Vasut · Mon May 28 17:22:47 2018 +0200
  8. 023b31b ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10 by Marek Vasut · Tue May 29 18:04:15 2018 +0200
  9. 4606fc7 SPDX: Fixup SPDX tags in a few new files by Tom Rini · Sun May 20 09:47:45 2018 -0400
  10. 402735b ARM: socfpga: Add DDR driver for Arria 10 by Tien Fong Chee · Tue Dec 05 15:58:02 2017 +0800