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git01.mediatek.com / filogic / uboot / 1b4bc156653438fc5e0a507d5d23c6a2e8e48c0c / arch / arm / dts / socfpga_cyclone5_vining_fpga-u-boot.dtsi
  1. b0fc4fd arm: socfpga: vining: Fix UDC controller phandle in DT by Marek Vasut · Tue Sep 14 05:25:34 2021 +0200
  2. 42de3a2 arm: socfpga: vining: Un-disable WDT in DT by Marek Vasut · Tue Sep 14 05:25:33 2021 +0200
  3. 8655f67 watchdog: designware: Convert to DM and DT probing by Marek Vasut · Thu Jun 27 01:19:23 2019 +0200
  4. a1c1ec1 ARM: socfpga: vining_fpga: Update DT by Marek Vasut · Thu Jun 27 00:19:32 2019 +0200
  5. 64a12bf arm: socfpga: gen5: add reset & sdr node to SPL devicetrees by Simon Goldschmidt · Fri Mar 01 20:12:29 2019 +0100
  6. a009fa7 dts: switch spi-flash to jedec, spi-nor compatible by Neil Armstrong · Sun Feb 10 10:16:20 2019 +0000
  7. 15616b5 dts: arm: socfpga: merge gen5 devicetrees from linux by Simon Goldschmidt · Fri Nov 02 11:54:52 2018 +0100