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git01.mediatek.com / filogic / uboot / 1a3732cb2575df75dcf83479a7d69266eff9745a / drivers / clk / sunxi / clk_h3.c
  1. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  2. 755e181 clk: sunxi: h3: Implement EPHY CLK and RESET by Jagan Teki · Thu Feb 28 00:26:59 2019 +0530
  3. 836631b clk: sunxi: Implement EMAC, GMAC clocks, resets by Jagan Teki · Thu Feb 28 00:26:57 2019 +0530
  4. bc12313 clk: sunxi: Implement SPI clocks, resets by Jagan Teki · Wed Feb 27 20:02:06 2019 +0530
  5. ddf33c1 sunxi: clk: add MMC gates/resets by Andre Przywara · Tue Jan 29 15:54:09 2019 +0000
  6. b490aa5 clk: sunxi: Implement UART resets by Jagan Teki · Sun Dec 30 21:37:31 2018 +0530
  7. 8cf08ea clk: sunxi: Implement UART clocks by Jagan Teki · Sun Dec 30 21:29:24 2018 +0530
  8. 2ee11ff clk: sunxi: Add Allwinner H3/H5 CLK driver by Jagan Teki · Thu Aug 02 15:43:02 2018 +0530