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git01.mediatek.com / filogic / uboot / 1a32b7af1bf244d4a1416377798c0568e32b8def / cpu / mpc85xx / spd_sdram.c
  1. 6c309b0 Empirically set cpo and clk_adjust for mpc85xx DDR2 support by Haiying Wang · Tue Jun 19 14:18:32 2007 -0400
  2. 30725fe MPC85xx BA bits not set for 3-bit bank address DIMM by Andy Fleming · Mon Aug 13 14:49:59 2007 -0500
  3. dadc6c9 85xx allow debugger to configure ddr. by Ed Swarthout · Fri Jul 27 01:50:48 2007 -0500
  4. 8c7adf4 Support 1G size on 8548 by Andy Fleming · Fri Feb 23 17:12:25 2007 -0600
  5. ce1f25f Only set ddrioovcr for 8548 rev1. by Andy Fleming · Fri Feb 23 16:28:46 2007 -0600
  6. 9782c55 Tweak DDR ECC error counter by Andy Fleming · Sat Feb 24 01:16:45 2007 -0600
  7. d46f6e7 Code cleanup by Wolfgang Denk · Tue Oct 24 15:32:57 2006 +0200
  8. ae13a64 Coding style changes to remove local varible blocks and reformat a bit nicer. by Jon Loeliger · Tue Oct 10 17:19:03 2006 -0500
  9. ebc7224 Fix style issues primarily in 85xx and 83xx boards. by Jon Loeliger · Mon Aug 01 13:20:47 2005 -0500
  10. 77a4f6e * Patch by Jon Loeliger, 2005-05-05 by Jon Loeliger · Mon Jul 25 14:05:07 2005 -0500
  11. 6d3c6d1 Patches by Josef Wagner, 29 Oct 2004: by wdenk · Sun Apr 03 22:35:21 2005 +0000
  12. 492b9e7 Patch by Jon Loeliger, 16 Jul 2004: by wdenk · Sun Aug 01 23:02:45 2004 +0000
  13. a445ddf Patches Part 1 by Jon Loeliger, 11 May 2004: by wdenk · Wed Jun 09 00:34:46 2004 +0000
  14. 9c53f40 * Patches by Xianghua Xiao, 15 Oct 2003: by wdenk · Wed Oct 15 23:53:47 2003 +0000