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git01.mediatek.com / filogic / uboot / 196b1efd55b71dfc6baca103fe8cdd8d56dea834 / drivers / clk / renesas / rcar-gen3-cpg.h
  1. 06c4f9b clk: renesas: Add R8A774A1 clock tables by Adam Ford · Tue Jun 30 09:30:08 2020 -0500
  2. 7841483 clk: renesas: Synchronize Gen3 tables with Linux 5.0 by Marek Vasut · Mon Mar 04 21:38:10 2019 +0100
  3. 69459b2 clk: renesas: Add PE clock handling by Marek Vasut · Thu May 31 19:47:42 2018 +0200
  4. 7ef12c2 clk: renesas: Pull Gen3 specific bits into separate header by Marek Vasut · Mon Jan 08 17:09:45 2018 +0100