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git01.mediatek.com / filogic / uboot / 17abed0a281d7efae0886bd07e43ce61367b23a1 / test / dm / clk_ccf.c
  1. b02e8dd clk: do not disable clock if it is critical by Claudiu Beznea · Mon Sep 07 17:46:35 2020 +0300
  2. c8c1600 clk: bind clk to new parent device by Claudiu Beznea · Mon Sep 07 17:46:34 2020 +0300
  3. e7ce74d clk: ccf: mux: change the get_rate helper by Dario Binacchi · Wed Jun 03 15:36:25 2020 +0200
  4. 1a62dc1 clk: set flags in the ccf registration routines by Dario Binacchi · Mon Apr 13 14:36:27 2020 +0200
  5. c98b802 dm: test: clk: add the test for the ccf gated clock by Dario Binacchi · Mon Apr 13 14:36:26 2020 +0200
  6. 974dccd dm: Rename DM test flags to make them more generic by Simon Glass · Tue Jul 28 19:41:12 2020 -0600
  7. 75c4d41 dm: core: Drop header files from dm/test.h by Simon Glass · Sun Jul 19 10:15:37 2020 -0600
  8. 8eec510 sandbox: clk: add clk enable/disable test code by Peng Fan · Wed Aug 21 13:35:19 2019 +0000
  9. 91f053f test: dm: clk_ccf: test composite clk by Peng Fan · Wed Jul 31 07:02:05 2019 +0000
  10. 8c0709b clk: sandbox: Add sandbox test code for Common Clock Framework [CCF] by Lukasz Majewski · Mon Jun 24 15:50:50 2019 +0200