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git01.mediatek.com / filogic / uboot / 166a047e272472c6b60ce4c0746fa995993451c8 / arch / arm / include / asm / arch-rockchip / cru_rk3588.h
  1. 166a047 clk: rockchip: rk3588: Set SPLL frequency during SPL stage by Heiko Stuebner · Wed May 22 19:31:29 2024 +0200
  2. 29e289c rockchip: rk3588: add constants for some register address spaces by Quentin Schulz · Mon Mar 11 13:01:55 2024 +0100
  3. b450590 rockchip: rk3588: Add support for sdmmc clocks in SPL by Jonas Karlman · Mon Apr 17 19:07:20 2023 +0000
  4. 9c9aab1 arm: rockchip: Add cru header for rk3588 by Jagan Teki · Mon Jan 30 20:27:33 2023 +0530