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git01.mediatek.com / filogic / uboot / 14916cf029b361df38ba78cf71bbd4730bb24a80 / include / asm-ppc / fsl_ddr_sdram.h
  1. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · Fri Nov 21 16:31:35 2008 +0800
  2. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · Fri Nov 21 16:31:29 2008 +0800
  3. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  4. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500