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git01.mediatek.com / filogic / uboot / 13a5d872471672426807353ea9c75fd8ba01bb10 / arch / mips / include / asm / mipsregs.h
  1. ecf0d79 MIPS: fix iand optimize setup of CP0 registers by Daniel Schwierzeck · Mon Feb 08 00:37:59 2016 +0100
  2. fcdc1fb MIPS: Hang if run on a secondary CPU by Paul Burton · Wed Sep 21 14:59:54 2016 +0100
  3. 8156078 MIPS: L2 cache support by Paul Burton · Wed Sep 21 11:18:54 2016 +0100
  4. 4f5561c MIPS: Preserve Config implementation-defined bits by Paul Burton · Wed Sep 21 11:18:50 2016 +0100
  5. a6dae71 MIPS: sync processor and register definitions with linux-4.4 by Daniel Schwierzeck · Tue Jan 12 21:48:26 2016 +0100
  6. 36c624a mips: Use unsigned int when reading c0 registers by Chris Packham · Tue Jul 14 22:54:41 2015 +1200
  7. f122b5a mips32: detect L1 cache sizes if they're not defined by Paul Burton · Fri Nov 08 11:18:42 2013 +0000
  8. 3cba3c1 Move architecture-specific includes to arch/$ARCH/include/asm by Peter Tyser · Mon Apr 12 22:28:08 2010 -0500[Renamed from include/asm-mips/mipsregs.h]
  9. 0fdd27e [MIPS] <asm/mipsregs.h>: Update coprocessor register access macros by Shinya Kuribayashi · Fri May 30 00:53:38 2008 +0900
  10. 179f974 [MIPS] <asm/mipsregs.h>: Update register / bit field definitions by Shinya Kuribayashi · Fri May 30 00:53:38 2008 +0900
  11. 43ce5b7 [MIPS] <asm/mipsregs.h>: CodinygStyle cleanups by Shinya Kuribayashi · Fri May 30 00:53:37 2008 +0900
  12. a1be476 Big white-space cleanup. by Wolfgang Denk · Tue May 20 16:00:29 2008 +0200
  13. 9b7f384 * Patch by Steven Scholz, 10 Oct 2003 - Add support for Altera FPGA ACEX1K by wdenk · Thu Oct 09 20:09:04 2003 +0000
  14. 57b2d80 * Code cleanup: by wdenk · Fri Jun 27 21:31:46 2003 +0000
  15. 4fc9569 * Add support for 16 MB flash configuration of TRAB board by wdenk · Fri Feb 28 00:49:47 2003 +0000