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git01.mediatek.com / filogic / uboot / 131ec9589dbc48193feca5d7ad41652f3993a1d1 / drivers / ram / stm32mp1 / stm32mp1_ddr.c
  1. 2ebc211 ram: stm32mp1: increase vdd2_ddr: buck2 for 32bits LPDDR by Patrick Delaunay · Fri Mar 06 11:14:03 2020 +0100
  2. bbee270 stm32mp1: ram: add interactive mode for DDR configuration by Patrick Delaunay · Wed Apr 10 14:09:27 2019 +0200
  3. 4175f45 stm32mp1: ram: add support for LPDDR2/LPDDR3 by Patrick Delaunay · Wed Apr 10 14:09:26 2019 +0200
  4. d892d27 stm32mp1: ram: update parameter array initialization by Patrick Delaunay · Wed Apr 10 14:09:25 2019 +0200
  5. 29e1a94 stm32mp1: ram: change ddr speed to kHz by Patrick Delaunay · Wed Apr 10 14:09:23 2019 +0200
  6. 1f98704 stm32mp1: ram: increase the delay after reset to 128 cycles by Patrick Delaunay · Wed Apr 10 14:09:22 2019 +0200
  7. 250bf90 stm32mp1: ram: update mask for operating mode by Patrick Delaunay · Wed Apr 10 14:09:21 2019 +0200
  8. 8b0c8a1 SPDX: Convert all of our multiple license tags to Linux Kernel style by Tom Rini · Sun May 06 18:27:01 2018 -0400
  9. 939d536 ram: stm32mp1: add driver by Patrick Delaunay · Mon Mar 12 10:46:11 2018 +0100