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git01.mediatek.com / filogic / uboot / 1123406ebbc1d72dd1f456ce29972a154f68f91a / arch / arm / cpu / armv7 / ls102xa / soc.c
  1. 1123406 fsl-layerscape: Consolidate registers space defination for CCI-400 bus by Ashish Kumar · Fri Aug 11 11:09:14 2017 +0530
  2. e15479b Convert CONFIG_FSL_DCU_FB to Kconfig by Sanchayan Maity · Tue Apr 11 11:12:09 2017 +0530
  3. 73e0b01 armv7: LS1021a: enable i-cache in start.S by Xiaoliang Yang · Wed Sep 14 11:36:14 2016 +0800
  4. 4b23ca8 fsl-layerscape: Add workaround for PCIe erratum A010315 by Hou Zhiqiang · Tue Aug 02 19:03:27 2016 +0800
  5. 5ac9a5c arm: fsl-layerscape: move forward the non-secure access permission setup by Hou Zhiqiang · Tue Aug 02 19:03:23 2016 +0800
  6. 6936492 armv7: ls102xa: Move smmu and stream id initialization into the common soc code by Alison Wang · Fri Feb 05 12:48:17 2016 +0800
  7. 96dae92 armv7/fsl-ls102xa: Workaround for DDR erratum A008514 by Yao Yuan · Sat Dec 05 14:59:13 2015 +0800
  8. 411fd29 armv7: ls102xa: cci-400: Enable snoop and DVM message requests. by Yao Yuan · Sat Dec 05 14:59:12 2015 +0800
  9. 1f28a4c arm: ls102xa: enable all the snoop signal for masters. by Yao Yuan · Sat Dec 05 14:59:11 2015 +0800
  10. e0f8f54 arm: ls1021a: merge SoC specific code in a separate file by Yao Yuan · Sat Dec 05 14:59:10 2015 +0800