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git01.mediatek.com
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filogic
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uboot
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10a61df5d7ad1f01e161b79b4e7a1f33180d574b
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drivers
/
clk
/
sifive
/
fu540-prci.c
ecefa5f
drivers: clk: add fu740 support
by Green Wan
· Thu May 27 06:52:08 2021 -0700
65130cd
dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()
by Simon Glass
· Mon Dec 28 20:34:56 2020 -0700
8a2b47f
dm: treewide: Rename auto_alloc_size members to be shorter
by Simon Glass
· Thu Dec 03 16:55:17 2020 -0700
1f4d206
clk: sifive: Include device_compat.h
by Sean Anderson
· Sun Oct 04 21:39:42 2020 -0400
e1ff6eb
sifive: reset: add DM based reset driver for SiFive SoC's
by Sagar Shrikant Kadam
· Wed Jul 29 02:36:13 2020 -0700
9158b39
fu540: prci: use common reset indexes defined in binding header
by Sagar Shrikant Kadam
· Wed Jul 29 02:36:11 2020 -0700
e848dba
clk: sifive: fu540-prci: Release ethernet clock reset
by Pragnesh Patel
· Fri May 29 11:33:31 2020 +0530
1790bce
clk: sifive: fu540-prci: Add ddr clock initialization
by Pragnesh Patel
· Fri May 29 11:33:30 2020 +0530
54ce0e0
clk: sifive: fu540-prci: Add clock enable and disable ops
by Pragnesh Patel
· Fri May 29 11:33:29 2020 +0530
dbd7954
common: Drop linux/delay.h from common header
by Simon Glass
· Sun May 10 11:40:11 2020 -0600
d66c5f7
dm: core: Require users of devres to include the header
by Simon Glass
· Mon Feb 03 07:36:15 2020 -0700
9a99add
clk: sifive: Sync-up main driver with upstream Linux
by Anup Patel
· Tue Jun 25 06:31:21 2019 +0000
83d5b50
clk: sifive: Sync-up DT bindings header with upstream Linux
by Anup Patel
· Tue Jun 25 06:31:15 2019 +0000
6f7b5a2
clk: sifive: Sync-up WRPLL library with upstream Linux
by Anup Patel
· Tue Jun 25 06:31:08 2019 +0000
00a156d
clk: sifive: Factor-out PLL library as separate module
by Anup Patel
· Tue Jun 25 06:31:02 2019 +0000
72be986
clk: sifive: fu540-prci: Change include order
by Jagan Teki
· Wed May 08 19:52:18 2019 +0530
42fdf08
clk: Add SiFive FU540 PRCI clock driver
by Anup Patel
· Mon Feb 25 08:14:49 2019 +0000