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git01.mediatek.com / filogic / uboot / 105bd899ce2a0b3b2a2fa1ce752eaea09c9a95bd / board / xes / common / fsl_8xxx_clk.c
  1. 4b08dd7 powerpc: P2020: Remove macro CONFIG_P2020 by York Sun · Fri Nov 18 11:08:43 2016 -0800
  2. bd8ec7e Coding Style cleanup: remove trailing white space by Wolfgang Denk · Mon Oct 07 13:07:26 2013 +0200
  3. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  4. 9a0709d XPedite5500 board support by John Schmoller · Fri Oct 22 00:20:34 2010 -0500
  5. 2b1a48d xes: Use proper IO access functions by Peter Tyser · Fri Aug 07 13:16:34 2009 -0500
  6. 281e41d xes: Update Freescale clock code to work with 86xx processors by Peter Tyser · Fri May 22 10:26:37 2009 -0500[Renamed (86%) from board/xes/common/fsl_8572_clk.c]
  7. 1c2b329 XPedite5370 board support by Peter Tyser · Wed Dec 17 16:36:23 2008 -0600