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git01.mediatek.com / filogic / uboot / 0f4011a402f4a4eb0382f03866807255e6c053c2 / arch / arm / cpu / armv7 / zynq / slcr.c
  1. 250e605 ARM: zynq: slcr: Dont modify the reserved bits by Siva Durga Prasad Paladugu · 10 years ago
  2. ec02820 ARM: zynq: ehci: Added USB host driver support by Michal Simek · 11 years ago
  3. 8d19162 ARM: zynq: Add MIO detection code by Michal Simek · 11 years ago
  4. bc73304 ARM: zynq: Setup correct slcr_lock value by Michal Simek · 11 years ago
  5. 7cffeb0 ARM: zynq: slcr: Fix incorrect commentary by Michal Simek · 11 years ago
  6. 90b8064 ARM: zynq: Fix sparse warnings in slcr.c by Michal Simek · 11 years ago
  7. 4dded98 net: zynq_gem: Calculate clock dividers dynamically by Soren Brinkmann · 11 years ago
  8. 3b5b992 net: zynq_gem: Move RCLK details out of driver by Soren Brinkmann · 11 years ago
  9. 11704c2 zynq: Add support to find bootmode by Jagannadha Sutradharudu Teki · 11 years ago
  10. 661ccfc zynq: slcr: Wait 100ms till clk is properly setup by Michal Simek · 12 years ago
  11. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · 11 years ago
  12. 15d654c fpga: zynq: Add support for loading bitstream by Michal Simek · 12 years ago
  13. d9f2c11 net: gem: Fix gem driver on 1Gbps LAN by Michal Simek · 12 years ago
  14. eb1dfa7 arm: zynq: Add SLCR support with system reset by Michal Simek · 12 years ago