1. 5efc934 riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree by Yanhong Wang · Wed Mar 29 11:42:23 2023 +0800
  2. 249ce73 riscv: Rename Andes cpu and board names by Leo Yu-Chi Liang · Tue Feb 14 20:42:49 2023 +0800
  3. c8481ef dts: automatically build necessary .dtb files by Rasmus Villemoes · Mon Jan 10 14:34:41 2022 +0100
  4. bd07fb4 riscv: qemu: Split devicetree files for qemu_riscv32/64 by Simon Glass · Thu Dec 16 20:59:12 2021 -0700
  5. 288ad1f board: sifive: drop stuff related to unmatched revision 1 by Zong Li · Tue Jul 20 14:26:08 2021 +0800
  6. bab770a riscv: dts: add dts for unmatched rev1 by Zong Li · Wed Jun 30 23:23:49 2021 +0800
  7. 2ef594d board: riscv: add openpiton-riscv64 SoC support by Tianrui Wei · Thu Jul 01 12:54:19 2021 +0800
  8. e552af3 riscv: dts: add SiFive Unmatched board support by Green Wan · Thu May 27 06:52:12 2021 -0700
  9. 1255ab8 riscv: qemu: Switch to use binman to generate u-boot.itb by Bin Meng · Mon May 10 20:23:39 2021 +0800
  10. eada910 riscv: dts: Sort build targets in alphabetical order by Bin Meng · Mon May 10 20:23:38 2021 +0800
  11. e9ead4a riscv: sifive: Rename fu540 board to unleashed by Bin Meng · Wed Mar 17 11:10:58 2021 +0800
  12. 5854c3d riscv: dts: Add device tree for Microchip Icicle Kit by Padmarao Begari · Fri Jan 15 08:20:39 2021 +0530
  13. d11b582 riscv: Add device tree for K210 and Sipeed Maix BitM by Sean Anderson · Wed Jun 24 06:41:23 2020 -0400
  14. a8ed626 riscv: dts: Add hifive-unleashed-a00 dts from Linux by Jagan Teki · Mon Nov 18 16:59:40 2019 +0530
  15. 5ca381e riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure by Rick Chen · Wed Apr 03 10:43:37 2019 +0800
  16. baaa062 riscv: dts: Add ae350_32.dts for RV32I by Rick Chen · Tue Nov 13 16:33:29 2018 +0800
  17. b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · Tue May 29 09:54:40 2018 +0800
  18. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  19. 2e4fc1b riscv: nx25: dts: Add AE250 dts to support RISC-V by Rick Chen · Tue Dec 26 13:55:50 2017 +0800