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git01.mediatek.com / filogic / uboot / 0db4b94f66612cda8487d9dc1835c7fdc3272633 / drivers / ram / stm32mp1 / stm32mp1_ddr.c
  1. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  2. a68e2d6 ram: stm32mp1: the property st, phy-cal becomes optional by Patrick Delaunay · Fri Mar 06 11:14:11 2020 +0100
  3. eca9bc0 ram: stm32mp1_ddr: fix self refresh disable during DQS training by Patrick Delaunay · Fri Mar 06 11:14:09 2020 +0100
  4. 2ebc211 ram: stm32mp1: increase vdd2_ddr: buck2 for 32bits LPDDR by Patrick Delaunay · Fri Mar 06 11:14:03 2020 +0100
  5. bbee270 stm32mp1: ram: add interactive mode for DDR configuration by Patrick Delaunay · Wed Apr 10 14:09:27 2019 +0200
  6. 4175f45 stm32mp1: ram: add support for LPDDR2/LPDDR3 by Patrick Delaunay · Wed Apr 10 14:09:26 2019 +0200
  7. d892d27 stm32mp1: ram: update parameter array initialization by Patrick Delaunay · Wed Apr 10 14:09:25 2019 +0200
  8. 29e1a94 stm32mp1: ram: change ddr speed to kHz by Patrick Delaunay · Wed Apr 10 14:09:23 2019 +0200
  9. 1f98704 stm32mp1: ram: increase the delay after reset to 128 cycles by Patrick Delaunay · Wed Apr 10 14:09:22 2019 +0200
  10. 250bf90 stm32mp1: ram: update mask for operating mode by Patrick Delaunay · Wed Apr 10 14:09:21 2019 +0200
  11. 8b0c8a1 SPDX: Convert all of our multiple license tags to Linux Kernel style by Tom Rini · Sun May 06 18:27:01 2018 -0400
  12. 939d536 ram: stm32mp1: add driver by Patrick Delaunay · Mon Mar 12 10:46:11 2018 +0100