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git01.mediatek.com / filogic / uboot / 0b0409c5f351aa54584c26bb53aa1d4cf0e5e827 / drivers / clk / clk_stm32mp1.c
  1. 3247081 clk: stm32: add hardware spinlock clock by Benjamin Gaignard · Tue Nov 27 13:49:51 2018 +0100
  2. 80cb568 stm32mp1: clk: support digital bypass by Patrick Delaunay · Mon Jul 16 10:41:46 2018 +0200
  3. 201f0d5 stm32mp1: clk: add ADC clock gating by Patrick Delaunay · Mon Jul 16 10:41:45 2018 +0200
  4. effe2b4 stm32mp1: clk: update Ethernet clock gating by Patrick Delaunay · Mon Jul 16 10:41:44 2018 +0200
  5. 8314d2c stm32mp1: clk: add LDTC and DSI clock support by Patrick Delaunay · Mon Jul 16 10:41:43 2018 +0200
  6. 5327d37 stm32mp1: clk: add common function pll_get_fvco by Patrick Delaunay · Mon Jul 16 10:41:42 2018 +0200
  7. a7c0fd6 stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro by Patrick Delaunay · Mon Jul 16 10:41:41 2018 +0200
  8. b139a5b misc: stm32: Add STM32MP1 support by Patrick Delaunay · Mon Jul 09 15:17:20 2018 +0200
  9. 4cb3b53 clk: stm32mp1: Add VREF clock gating by Fabrice Gasnier · Thu Apr 26 17:00:47 2018 +0200
  10. 8b0c8a1 SPDX: Convert all of our multiple license tags to Linux Kernel style by Tom Rini · Sun May 06 18:27:01 2018 -0400
  11. bf7d944 clock: stm32mp1: add stgen clock source change support by Patrick Delaunay · Tue Mar 20 11:41:25 2018 +0100
  12. f11398e clk: stm32mp1: add clock tree initialization by Patrick Delaunay · Mon Mar 12 10:46:16 2018 +0100
  13. e6ab627 clk: add driver for stm32mp1 by Patrick Delaunay · Mon Mar 12 10:46:15 2018 +0100