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filogic
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uboot
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0ab8678613ec95e1104a8aa92ba9f3afa5067c1e
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arch
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riscv
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cpu
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mtrap.S
6c6315e
riscv: Align the trap handler to 64 bytes
by Samuel Holland
· Tue Oct 31 00:35:41 2023 -0500
b6b9900
riscv: Remove common.h usage
by Tom Rini
· Thu Oct 12 19:03:59 2023 -0400
e8b46a1
riscv: Add option to print registers on exception
by Sean Anderson
· Wed Dec 25 00:27:44 2019 -0500
1f46f6d
riscv: Return to previous privilege level after trap handling
by Bin Meng
· Wed Dec 12 06:12:43 2018 -0800
ea95452
riscv: Fix context restore before returning from trap handler
by Bin Meng
· Wed Dec 12 06:12:42 2018 -0800
2e128a7
riscv: Move trap handler codes to mtrap.S
by Bin Meng
· Wed Dec 12 06:12:41 2018 -0800