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git01.mediatek.com / filogic / uboot / 09e9213fef116583deb94008b1df8b23e82cae0c / drivers / clk / aspeed
  1. d7f3789 aspeed: ast2500: fix D2-PLL clock setting in RGMII mode by Cédric Le Goater · 6 years ago
  2. 62b4bfd aspeed: ast2500: fix missing break in D2PLL clock enablement by Cédric Le Goater · 6 years ago
  3. d6e53c7 drivers: cosmetic: Convert SPDX license tags to Linux Kernel style by Patrick Delaunay · 6 years ago
  4. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · 7 years ago
  5. ba1dea4 dm: Rename dev_addr..() functions by Simon Glass · 8 years ago
  6. a91f1d2 aspeed: Refactor SCU to use consistent mask & shift by maxims@google.com · 8 years ago
  7. 15016af aspeed: Add support for Clocks needed by MACs by maxims@google.com · 8 years ago
  8. 995167b aspeed: Add P-Bus clock in ast2500 clock driver by maxims@google.com · 8 years ago
  9. adea66c aspeed: Make SCU lock/unlock functions part of SCU API by maxims@google.com · 8 years ago
  10. d067217 aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation by maxims@google.com · 8 years ago
  11. 2d5a2ad aspeed: Add basic ast2500-specific drivers and configuration by maxims@google.com · 8 years ago