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git01.mediatek.com / filogic / uboot / 07a8af37f5c527f3000b10fcdf57bab72ae29898 / include / asm-ppc / fsl_ddr_sdram.h
  1. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  2. 30cb145 32bit BUg fix for DDR2 on 8572 by Poonam_Aggrwal-b10812 · Sun Jan 04 08:46:38 2009 +0530
  3. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · Fri Nov 21 16:31:35 2008 +0800
  4. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · Fri Nov 21 16:31:29 2008 +0800
  5. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  6. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500