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git01.mediatek.com / filogic / uboot / 073e23e2869a013a4e7dd427f3611997cce53d95 / arch / arm / mach-sunxi / clock_sun6i.c
  1. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  2. dbd7954 common: Drop linux/delay.h from common header by Simon Glass · Sun May 10 11:40:11 2020 -0600
  3. b01dc98 sunxi: Fix pll1 clock calculation by Stefan Mavrodiev · Wed Jul 31 16:15:52 2019 +0300
  4. 05e7220 sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD by Icenowy Zheng · Sun Oct 28 14:26:12 2018 -0700
  5. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  6. 883b3c0 sunxi: switch PRCM to non-secure on H3/H5 SoCs by Icenowy Zheng · Thu Jul 20 14:00:32 2017 +0800
  7. 3279661 sunxi: add clock configuration of R40 sata by Icenowy Zheng · Mon May 01 14:31:56 2017 +0800
  8. 9b4ca92 sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs by Jernej Skrabec · Mon Mar 27 19:22:31 2017 +0200
  9. 143ef79 sunxi: Use H3/A64 DRAM initialization code for R40 by Chen-Yu Tsai · Thu Dec 01 19:09:57 2016 +0800
  10. 5eddcbb sunxi: Set PLL lock enable bits for R40 by Chen-Yu Tsai · Wed Nov 30 16:54:34 2016 +0800
  11. 5fb9743 sunxi: prepare for sharing MACH_SUN8I_H3 config symbol by Andre Przywara · Thu Feb 16 01:20:27 2017 +0000
  12. f613817 sunxi: A64: use H3 DRAM initialization code for A64 as well by Jens Kuske · Mon Jan 02 11:48:42 2017 +0000
  13. ced4a9a sunxi: clocks: Use the correct pattern register for PLL11 by Philipp Tomsich · Mon Jan 02 11:48:41 2017 +0000
  14. 79b59ef sun6i: Restrict some register initialization to Allwinner A31 SoC by Andre Przywara · Mon Jan 02 11:48:25 2017 +0000
  15. 213407e sunxi: Tune H3 DRAM PLL to improve lock time by Jens Kuske · Fri Aug 19 13:40:46 2016 +0200
  16. 8dd84a7 sunxi: Move cpu independent code to mach directory by Alexander Graf · Tue Mar 29 17:29:06 2016 +0200[Renamed from arch/arm/cpu/armv7/sunxi/clock_sun6i.c]
  17. 7969677 sunxi: Fix clock_twi_onoff for sun8i-a83 by Hans de Goede · Wed Mar 16 20:57:28 2016 +0100
  18. f946a87 sunxi: Fix clock_twi_onoff for sun6i by Hans de Goede · Wed Mar 16 20:44:51 2016 +0100
  19. 6daddfe sunxi: Support H3 CCU security switches by Chen-Yu Tsai · Wed Jan 06 15:13:07 2016 +0800
  20. 8d3d7c1 sunxi: Add support for the I2C controller which is part of the PRCM by Jelle van der Waa · Thu Jan 14 14:06:26 2016 +0100
  21. 08f391c sunxi: twi: Enable clocks on sun7i by Olliver Schinagl · Thu Dec 03 17:49:28 2015 +0100
  22. 2b8bd91 sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3 by Siarhei Siamashka · Fri Nov 20 07:07:48 2015 +0200
  23. d6eaadc sun6i: clock: Add support for the mipi pll by Hans de Goede · Sat Aug 08 14:05:35 2015 +0200
  24. 957a72729 sunxi: clock: Add clock_get_pll3() helper function by Hans de Goede · Sat Aug 08 12:36:44 2015 +0200
  25. 0fdbe20 sunxi: Add support for A33 PLL11 (second DRAM pll) by Hans de Goede · Sun Apr 12 11:46:41 2015 +0200
  26. 627bc69 sunxi: Drop pll6 setting from clock_init_uart by Hans de Goede · Wed Jan 14 19:28:38 2015 +0100
  27. 645d4d5 sunxi: Fix PLL1 running at half speed on sun8i by Hans de Goede · Sat Dec 27 17:56:59 2014 +0100
  28. 0bfa774 sun6i: clock_set_pll5: Calculate k and m rather then hardcoding them by Hans de Goede · Sun Dec 07 21:09:31 2014 +0100
  29. 0cbc4cb sun6i: Add a sigma_delta_enable paramter to clock_set_pll5() by Hans de Goede · Sun Nov 30 11:58:17 2014 +0100
  30. 70d7ab5 sunxi: Add video pll clock functions by Hans de Goede · Sat Nov 08 14:07:27 2014 +0100
  31. c27d68d sun6i: Add clock functions needed for SPL / DRAM init by Hans de Goede · Sat Oct 25 20:16:33 2014 +0200
  32. 6ee6388 ARM: sunxi: Add support for using R_UART as console by Chen-Yu Tsai · Wed Oct 22 16:47:47 2014 +0800
  33. 3a04542 ARM: sun6i: Add clock support by Chen-Yu Tsai · Fri Oct 03 20:16:25 2014 +0800