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git01.mediatek.com / filogic / uboot / 06a2234f7004de504d5e6883f293259e4e734bfc / drivers / clk / microchip / mpfs_clk.h
  1. 54713d6 clk: microchip: mpfs: support new syscon based devicetree configuration by Conor Dooley · Wed Oct 23 11:17:52 2024 +0100
  2. 73a1d60 clk: microchip: mpfs: fix periph clk parentage by Conor Dooley · Tue Oct 25 08:58:47 2022 +0100
  3. d4bbef0 clk: microchip: mpfs: fix reference clock handling by Conor Dooley · Tue Oct 25 08:58:46 2022 +0100
  4. 4a182e0 clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() by Conor Dooley · Tue Oct 25 08:58:45 2022 +0100
  5. 47b4c02 doc: replace @return by Return: by Heinrich Schuchardt · Wed Jan 19 18:05:50 2022 +0100
  6. 0c4ae80 clk: Add Microchip PolarFire SoC clock driver by Padmarao Begari · Fri Jan 15 08:20:38 2021 +0530