Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <asm/mmu.h> |
| 8 | |
| 9 | struct fsl_e_tlb_entry tlb_table[] = { |
| 10 | /* TLB 0 - for temp stack in cache */ |
| 11 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, |
| 12 | CONFIG_SYS_INIT_RAM_ADDR_PHYS, |
| 13 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 14 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 15 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , |
| 16 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, |
| 17 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 18 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 19 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , |
| 20 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, |
| 21 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 22 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 23 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , |
| 24 | CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, |
| 25 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 26 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 27 | |
| 28 | /* TLB 1 */ |
| 29 | /* *I*** - Covers boot page */ |
| 30 | SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
| 31 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, |
| 32 | 0, 0, BOOKE_PAGESZ_4K, 1), |
| 33 | |
| 34 | /* *I*G* - CCSRBAR */ |
| 35 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
| 36 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 37 | 0, 1, BOOKE_PAGESZ_1M, 1), |
| 38 | |
Scott Wood | c4f0d00 | 2012-09-20 19:05:12 -0500 | [diff] [blame] | 39 | #ifndef CONFIG_SPL_BUILD |
Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 40 | /* W**G* - Flash/promjet, localbus */ |
| 41 | /* This will be changed to *I*G* after relocation to RAM. */ |
| 42 | SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, |
| 43 | MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, |
| 44 | 0, 2, BOOKE_PAGESZ_64M, 1), |
| 45 | |
| 46 | #ifdef CONFIG_PCI |
| 47 | /* *I*G* - PCI memory 1.5G */ |
| 48 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, |
| 49 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 50 | 0, 3, BOOKE_PAGESZ_1G, 1), |
| 51 | |
| 52 | /* *I*G* - PCI I/O effective: 192K */ |
| 53 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, |
| 54 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 55 | 0, 4, BOOKE_PAGESZ_256K, 1), |
| 56 | #endif |
| 57 | |
| 58 | #ifdef CONFIG_VSC7385_ENET |
| 59 | /* *I*G - VSC7385 Switch */ |
| 60 | SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, |
| 61 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 62 | 0, 5, BOOKE_PAGESZ_1M, 1), |
| 63 | #endif |
| 64 | |
| 65 | SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, |
| 66 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 67 | 0, 6, BOOKE_PAGESZ_1M, 1), |
Scott Wood | c4f0d00 | 2012-09-20 19:05:12 -0500 | [diff] [blame] | 68 | #endif /* not SPL */ |
Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 69 | |
| 70 | #ifdef CONFIG_SYS_NAND_BASE |
| 71 | /* *I*G - NAND */ |
| 72 | SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
| 73 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 74 | 0, 7, BOOKE_PAGESZ_1M, 1), |
| 75 | #endif |
| 76 | |
Tom Rini | f8f6b32 | 2022-05-21 14:44:28 -0400 | [diff] [blame] | 77 | #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) |
Pali Rohár | cca5828 | 2022-04-07 12:16:18 +0200 | [diff] [blame] | 78 | /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */ |
Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 79 | SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |
York Sun | 05204d0 | 2017-12-05 10:57:54 -0800 | [diff] [blame] | 80 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, |
Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 81 | 0, 8, BOOKE_PAGESZ_1G, 1), |
| 82 | |
Priyanka Jain | b1d2441 | 2020-09-21 11:56:39 +0530 | [diff] [blame] | 83 | #if defined(CONFIG_TARGET_P1020RDB_PD) |
Pali Rohár | cca5828 | 2022-04-07 12:16:18 +0200 | [diff] [blame] | 84 | /* **M** - 2G DDR on P1020MBG, map the second 1G */ |
Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 85 | SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, |
| 86 | CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, |
Pali Rohár | cca5828 | 2022-04-07 12:16:18 +0200 | [diff] [blame] | 87 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, |
Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 88 | 0, 9, BOOKE_PAGESZ_1G, 1), |
Priyanka Jain | b1d2441 | 2020-09-21 11:56:39 +0530 | [diff] [blame] | 89 | #endif |
Scott Wood | 03fedda | 2012-10-12 18:02:24 -0500 | [diff] [blame] | 90 | #endif /* RAMBOOT/SPL */ |
Ying Zhang | 28027d7 | 2013-09-06 17:30:56 +0800 | [diff] [blame] | 91 | |
| 92 | #ifdef CONFIG_SYS_INIT_L2_ADDR |
Pali Rohár | c2b77f8 | 2022-07-27 17:21:28 +0200 | [diff] [blame] | 93 | /* ***G - L2SRAM */ |
Ying Zhang | 28027d7 | 2013-09-06 17:30:56 +0800 | [diff] [blame] | 94 | SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, |
| 95 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, |
Ying Zhang | b8b404d | 2013-09-06 17:30:58 +0800 | [diff] [blame] | 96 | 0, 11, BOOKE_PAGESZ_256K, 1), |
| 97 | #if CONFIG_SYS_L2_SIZE >= (256 << 10) |
| 98 | SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, |
| 99 | CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, |
Pali Rohár | c2b77f8 | 2022-07-27 17:21:28 +0200 | [diff] [blame] | 100 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, |
Ying Zhang | b8b404d | 2013-09-06 17:30:58 +0800 | [diff] [blame] | 101 | 0, 12, BOOKE_PAGESZ_256K, 1) |
| 102 | #endif |
Ying Zhang | 28027d7 | 2013-09-06 17:30:56 +0800 | [diff] [blame] | 103 | #endif |
Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 104 | }; |
| 105 | |
| 106 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |