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git01.mediatek.com / filogic / uboot / fe27eabe1fb3444ce7d8c9c5c84af876411c8f07 / . / arch / arm / mach-k3 / arm64-mmu.c
blob: 0e07b1b7ce0fa1ddd2be295ff2a9d1e868c74fee [file] [log] [blame]
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * K3: ARM64 MMU setup
4 *
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]5 * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]6 * Lokesh Vutla <lokeshvutla@ti.com>
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]7 * Suman Anna <s-anna@ti.com>
Michal Simek7f60b232019-01-17 08:22:43 +0100[diff] [blame]8 * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]9 *
10 */
11
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]12#include <asm/system.h>
13#include <asm/armv8/mmu.h>
14
Andrew Davis52454102023-11-28 11:05:28 -0600[diff] [blame]15struct mm_region k3_mem_map[] = {
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]16 {
17 .virt = 0x0UL,
18 .phys = 0x0UL,
19 .size = 0x80000000UL,
20 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
21 PTE_BLOCK_NON_SHARE |
22 PTE_BLOCK_PXN | PTE_BLOCK_UXN
23 }, {
24 .virt = 0x80000000UL,
25 .phys = 0x80000000UL,
Andrew Davisa55e4d42023-11-28 11:05:26 -0600[diff] [blame]26 .size = 0x1e780000UL,
Suman Annaf359afb2019-09-04 16:01:49 +0530[diff] [blame]27 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
28 PTE_BLOCK_INNER_SHARE
29 }, {
30 .virt = 0xa0000000UL,
31 .phys = 0xa0000000UL,
Andrew Davis2e9044a2023-11-28 11:05:27 -0600[diff] [blame]32 .size = 0x60000000UL,
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]33 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
34 PTE_BLOCK_INNER_SHARE
35 }, {
36 .virt = 0x880000000UL,
37 .phys = 0x880000000UL,
38 .size = 0x80000000UL,
39 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
40 PTE_BLOCK_INNER_SHARE
41 }, {
Vignesh Raghavendraf2716382020-02-04 11:09:49 +0530[diff] [blame]42 .virt = 0x500000000UL,
43 .phys = 0x500000000UL,
Sekhar Noridd507952024-01-09 14:15:51 +0530[diff] [blame]44 .size = 0x380000000UL,
Vignesh Raghavendraf2716382020-02-04 11:09:49 +0530[diff] [blame]45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_NON_SHARE |
47 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48 }, {
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]49 /* List terminator */
50 0,
51 }
52};
53
Andrew Davis52454102023-11-28 11:05:28 -0600[diff] [blame]54struct mm_region *mem_map = k3_mem_map;