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git01.mediatek.com / filogic / uboot / fe1723f623073463144af9a73a6f3f597ece0baf / . / arch / arc / Kconfig
blob: c044ad4de61d67abe7c33a58b98110adcb243009 [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]1menu "ARC architecture"
2 depends on ARC
3
4config SYS_ARCH
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]5 default "arc"
6
Alexey Brodkin93206d22015-02-03 13:58:20 +0300[diff] [blame]7config USE_PRIVATE_LIBGCC
8 default y
9
Alexey Brodkin7739f9f2014-12-25 18:47:45 +0300[diff] [blame]10config SYS_CPU
Alexey Brodkine41a3d52015-01-13 18:35:46 +0300[diff] [blame]11 default "arcv1" if ISA_ARCOMPACT
12 default "arcv2" if ISA_ARCV2
Alexey Brodkin7739f9f2014-12-25 18:47:45 +0300[diff] [blame]13
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]14choice
Alexey Brodkine41a3d52015-01-13 18:35:46 +0300[diff] [blame]15 prompt "ARC Instruction Set"
16 default ISA_ARCOMPACT
17
18config ISA_ARCOMPACT
19 bool "ARCompact ISA"
20 help
21 The original ARC ISA of ARC600/700 cores
22
23config ISA_ARCV2
24 bool "ARC ISA v2"
25 help
26 ISA for the Next Generation ARC-HS cores
27
28endchoice
29
30choice
Alexey Brodkinf431e262015-02-03 13:58:11 +0300[diff] [blame]31 prompt "CPU selection"
Alexey Brodkine41a3d52015-01-13 18:35:46 +0300[diff] [blame]32 default CPU_ARC770D if ISA_ARCOMPACT
33 default CPU_ARCHS38 if ISA_ARCV2
Alexey Brodkinf431e262015-02-03 13:58:11 +0300[diff] [blame]34
35config CPU_ARC750D
36 bool "ARC 750D"
37 select ARC_MMU_V2
Alexey Brodkine41a3d52015-01-13 18:35:46 +0300[diff] [blame]38 depends on ISA_ARCOMPACT
Alexey Brodkinf431e262015-02-03 13:58:11 +0300[diff] [blame]39 help
40 Choose this option to build an U-Boot for ARC750D CPU.
41
42config CPU_ARC770D
43 bool "ARC 770D"
44 select ARC_MMU_V3
Alexey Brodkine41a3d52015-01-13 18:35:46 +0300[diff] [blame]45 depends on ISA_ARCOMPACT
Alexey Brodkinf431e262015-02-03 13:58:11 +0300[diff] [blame]46 help
47 Choose this option to build an U-Boot for ARC770D CPU.
48
Alexey Brodkine41a3d52015-01-13 18:35:46 +0300[diff] [blame]49config CPU_ARCEM6
50 bool "ARC EM6"
51 select ARC_MMU_ABSENT
52 depends on ISA_ARCV2
53 help
54 Next Generation ARC Core based on ISA-v2 ISA without MMU.
55
56config CPU_ARCHS36
57 bool "ARC HS36"
58 select ARC_MMU_ABSENT
59 depends on ISA_ARCV2
60 help
61 Next Generation ARC Core based on ISA-v2 ISA without MMU.
62
63config CPU_ARCHS38
64 bool "ARC HS38"
65 select ARC_MMU_V4
66 depends on ISA_ARCV2
67 help
68 Next Generation ARC Core based on ISA-v2 ISA with MMU.
69
Alexey Brodkinf431e262015-02-03 13:58:11 +0300[diff] [blame]70endchoice
71
72choice
73 prompt "MMU Version"
74 default ARC_MMU_V3 if CPU_ARC770D
75 default ARC_MMU_V2 if CPU_ARC750D
Alexey Brodkine41a3d52015-01-13 18:35:46 +0300[diff] [blame]76 default ARC_MMU_ABSENT if CPU_ARCEM6
77 default ARC_MMU_ABSENT if CPU_ARCHS36
78 default ARC_MMU_V4 if CPU_ARCHS38
79
80config ARC_MMU_ABSENT
81 bool "No MMU"
82 help
83 No MMU
Alexey Brodkinf431e262015-02-03 13:58:11 +0300[diff] [blame]84
85config ARC_MMU_V2
86 bool "MMU v2"
87 depends on CPU_ARC750D
88 help
89 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
90 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
91
92config ARC_MMU_V3
93 bool "MMU v3"
94 depends on CPU_ARC770D
95 help
96 Introduced with ARC700 4.10: New Features
97 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
98 Shared Address Spaces (SASID)
99
Alexey Brodkine41a3d52015-01-13 18:35:46 +0300[diff] [blame]100config ARC_MMU_V4
101 bool "MMU v4"
102 depends on CPU_ARCHS38
103 help
104 Introduced as a part of ARC HS38 release.
105
Alexey Brodkinf431e262015-02-03 13:58:11 +0300[diff] [blame]106endchoice
107
Alexey Brodkincbd76c32015-02-03 13:58:14 +0300[diff] [blame]108config CPU_BIG_ENDIAN
109 bool "Enable Big Endian Mode"
110 default n
111 help
112 Build kernel for Big Endian Mode of ARC CPU
113
Alexey Brodkin6b95cca2015-02-03 13:58:13 +0300[diff] [blame]114config SYS_ICACHE_OFF
115 bool "Do not use Instruction Cache"
116 default n
117
118config SYS_DCACHE_OFF
119 bool "Do not use Data Cache"
120 default n
121
122config ARC_CACHE_LINE_SHIFT
123 int "Cache Line Length (as power of 2)"
124 range 5 7
125 default "6"
Alexey Brodkinbc9f1972015-03-17 14:26:43 +0300[diff] [blame]126 depends on !SYS_DCACHE_OFF || !SYS_ICACHE_OFF
Alexey Brodkin6b95cca2015-02-03 13:58:13 +0300[diff] [blame]127 help
128 Starting with ARC700 4.9, Cache line length is configurable,
129 This option specifies "N", with Line-len = 2 power N
130 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
131 Linux only supports same line lengths for I and D caches.
132
Alexey Brodkinf431e262015-02-03 13:58:11 +0300[diff] [blame]133choice
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]134 prompt "Target select"
135
Alexey Brodkinbc9f1972015-03-17 14:26:43 +0300[diff] [blame]136config TARGET_DUMMY
137 bool "Dummy target"
138 help
139 Please select one of real target boards below!
140 This target is only meant to force "makedefconfig" to put
141 TARGET_xxx in defconfig even this is the first target from the list
142 below.
143
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]144config TARGET_TB100
145 bool "Support tb100"
146
147config TARGET_ARCANGEL4
148 bool "Support arcangel4"
149
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]150config TARGET_AXS101
151 bool "Support axs101"
152
153endchoice
154
155source "board/abilis/tb100/Kconfig"
156source "board/synopsys/Kconfig"
157source "board/synopsys/axs101/Kconfig"
158
159endmenu