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git01.mediatek.com / filogic / uboot / 55a4c155cdb452b707165c46151961333085f080 / . / board / xilinx / zynqmp / zynqmp-e-a2197-00-revA / psu_init_gpl.c
blob: 40d9279378ba4240fb89cd159cf55c3cc32e9648 [file] [log] [blame]
Michal Simekb1783812021-09-24 15:06:18 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
4 */
5
6#include <asm/arch/psu_init_gpl.h>
7#include <xil_io.h>
8
9static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
10 u32 lane2_protocol, u32 lane2_rate,
11 u32 lane1_protocol, u32 lane1_rate,
12 u32 lane0_protocol, u32 lane0_rate);
13
14static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly,
15 int d_lock_cnt, int d_lfhf, int d_cp, int d_res);
16
17static unsigned long psu_pll_init_data(void)
18{
19 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
20 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
21 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
22 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
23 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
24 mask_poll(0xFF5E0040, 0x00000002U);
25 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
26 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
27 psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
28 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
29 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
30 psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
31 psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
32 psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
33 psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
34 mask_poll(0xFF5E0040, 0x00000001U);
35 psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
36 psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
37 psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
38 psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
39 psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
40 psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
41 psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
42 psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
43 mask_poll(0xFD1A0044, 0x00000001U);
44 psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
45 psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
46 psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
47 psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
48 psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
49 psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
50 psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
51 psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
52 mask_poll(0xFD1A0044, 0x00000002U);
53 psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
54 psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
55 psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
56 psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
57 psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
58 psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
59 psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
60 psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
61 mask_poll(0xFD1A0044, 0x00000004U);
62 psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
63 psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
64 psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
65
66 return 1;
67}
68
69static unsigned long psu_clock_init_data(void)
70{
71 psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U);
72 psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U);
73 psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U);
74 psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
75 psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
76 psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
77 psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
78 psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
79 psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
80 psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
81 psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
82 psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
83 psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
84 psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
85 psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
86 psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
87 psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
88 psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
89 psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
90 psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
91 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
92 psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
93 psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
94 psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
95 psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
96 psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
97 psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
98 psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
99 psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
100 psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
101 psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
102 psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
103 psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
104 psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
105 psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
106 psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
107
108 return 1;
109}
110
111static unsigned long psu_ddr_init_data(void)
112{
113 psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
114 psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U);
115 psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
116 psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U);
117 psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U);
118 psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
119 psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
120 psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
121 psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
122 psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
123 psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U);
124 psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
125 psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
126 psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
127 psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
128 psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U);
129 psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
130 psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
131 psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U);
132 psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
133 psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
134 psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
135 psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
136 psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
137 psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
138 psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U);
139 psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U);
140 psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1A10U);
141 psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U);
142 psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU);
143 psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U);
144 psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U);
145 psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U);
146 psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U);
147 psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
148 psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
149 psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
150 psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U);
151 psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U);
152 psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU);
153 psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
154 psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
155 psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
156 psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U);
157 psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
158 psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
159 psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U);
160 psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
161 psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
162 psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
163 psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
164 psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
165 psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
166 psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
167 psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U);
168 psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
169 psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
170 psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
171 psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
172 psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
173 psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
174 psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
175 psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
176 psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
177 psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
178 psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
179 psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
180 psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
181 psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
182 psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
183 psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
184 psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
185 psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
186 psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
187 psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
188 psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
189 psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
190 psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
191 psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
192 psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
193 psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
194 psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
195 psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
196 psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
197 psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
198 psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
199 psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
200 psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
201 psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
202 psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
203 psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
204 psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
205 psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
206 psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
207 psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
208 psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
209 psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
210 psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
211 psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
212 psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
213 psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
214 psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
215 psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
216 psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
217 psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
218 psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
219 psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
220 psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
221 psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
222 psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
223 psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
224 psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
225 psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
226 psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
227 psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
228 psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
229 psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
230 psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
231 psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U);
232 psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
233 psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
234 psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
235 psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
236 psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
237 psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
238 psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
239 psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U);
240 psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
241 psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U);
242 psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0711U);
243 psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U);
244 psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
245 psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU);
246 psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU);
247 psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U);
248 psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
249 psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
250 psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
251 psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
252 psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
253 psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U);
254 psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U);
255 psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
256 psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
257 psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
258 psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
259 psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
260 psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U);
261 psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
262 psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
263 psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
264 psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
265 psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
266 psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
267 psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
268 psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
269 psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
270 psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
271 psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
272 psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
273 psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
274 psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
275 psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
276 psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
277 psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
278 psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
279 psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
280 psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
281 psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
282 psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
283 psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U);
284 psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
285 psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
286 psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
287 psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
288 psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
289 psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
290 psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
291 psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
292 psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
293 psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
294 psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
295 psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
296 psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
297 psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
298 psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
299 psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
300 psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
301 psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
302 psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
303 psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U);
304 psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
305 psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
306 psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
307 psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
308 psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
309 psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U);
310 psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
311 psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
312 psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
313 psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
314 psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
315 psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U);
316 psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U);
317 psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
318 psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
319 psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
320 psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
321 psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
322 psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
323 psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U);
324 psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
325 psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
326 psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
327 psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
328 psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
329 psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
330 psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U);
331 psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
332 psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
333 psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
334 psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
335 psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
336 psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
337 psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U);
338 psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
339 psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
340 psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
341 psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
342 psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
343 psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
344 psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U);
345 psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
346 psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
347 psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
348 psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
349 psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
350 psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
351 psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
352 psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
353 psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
354 psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
355 psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
356 psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
357 psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
358 psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
359 psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
360 psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
361 psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
362 psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
363 psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
364 psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
365 psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
366 psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
367 psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
368 psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
369 psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
370 psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
371 psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
372 psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
373
374 return 1;
375}
376
377static unsigned long psu_ddr_qos_init_data(void)
378{
379 psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
380 psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
381 psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
382 psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
383 psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
384 psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
385 psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
386 psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
387 psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
388 psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
389 psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
390 psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
391 psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
392 psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
393
394 return 1;
395}
396
397static unsigned long psu_mio_init_data(void)
398{
399 psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U);
400 psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U);
401 psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U);
402 psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U);
403 psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U);
404 psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U);
405 psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U);
406 psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
407 psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
408 psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U);
409 psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U);
410 psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U);
411 psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
412 psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
413 psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U);
414 psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U);
415 psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U);
416 psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
417 psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
418 psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
419 psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
420 psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
421 psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
422 psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
423 psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
424 psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
425 psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
426 psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
427 psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
428 psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
429 psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
430 psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
431 psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
432 psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
433 psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U);
434 psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U);
435 psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
436 psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
437 psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U);
438 psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U);
439 psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
440 psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
441 psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
442 psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
443 psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
444 psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
445 psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
446 psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
447 psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
448 psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
449 psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
450 psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
451 psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000000U);
452 psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000000U);
453 psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000000U);
454 psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000000U);
455 psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000000U);
456 psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000000U);
457 psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000000U);
458 psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000000U);
459 psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000000U);
460 psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000000U);
461 psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000000U);
462 psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000000U);
463 psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U);
464 psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U);
465 psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U);
466 psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U);
467 psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U);
468 psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U);
469 psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U);
470 psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U);
471 psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U);
472 psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U);
473 psu_mask_write(0xFF180128, 0x000000FEU, 0x00000000U);
474 psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000000U);
475 psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
476 psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
477 psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00000000U);
478 psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00002040U);
479 psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U);
480 psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
481 psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
482 psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
483 psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
484 psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
485 psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
486 psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
487 psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
488 psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
489 psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
490 psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
491 psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
492 psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
493 psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
494 psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
495 psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
496 psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
497 psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
498 psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
499
500 return 1;
501}
502
503static unsigned long psu_peripherals_pre_init_data(void)
504{
505 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
506
507 return 1;
508}
509
510static unsigned long psu_peripherals_init_data(void)
511{
512 psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
513 psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
514 psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
515 psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
516 psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
517 psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
518 psu_mask_write(0xFF180320, 0x33840000U, 0x00800000U);
519 psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
520 psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
521 psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
522 psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
523 psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
Michal Simekb1783812021-09-24 15:06:18 +0200[diff] [blame]524 psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
525 psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
526 psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
527 psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
528 psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
529 psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
530 psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
531 return 1;
532}
533
534static unsigned long psu_serdes_init_data(void)
535{
536 psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
537 psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
538 psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
539 psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
540 psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
541 psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
542 psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
543 psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
544 psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
545 psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
546 psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
547 psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U);
548 psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U);
549 psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U);
550 psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
551 psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
552 psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
553 psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU);
554 psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
555 psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU);
556 psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
557 psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
558 psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
559 psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
560 psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
561 psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
562 psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
563 psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
564 psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
565 psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
566 psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
567 psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
568 psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
569 psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
570 psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
571 psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
572 psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
573 psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
574 psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
575 psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
576 psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
577 psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
578 psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
579 psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
580 psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
581 psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
582 psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
583 psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
584 psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
585
586 serdes_illcalib(0, 0, 0, 0, 0, 0, 5, 0);
587 psu_mask_write(0xFD410010, 0x00000007U, 0x00000005U);
588 psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
589 psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
590
591 return 1;
592}
593
594static unsigned long psu_resetout_init_data(void)
595{
596 psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
597 psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
598 mask_poll(0xFD4023E4, 0x00000010U);
599
600 return 1;
601}
602
603static unsigned long psu_resetin_init_data(void)
604{
605 psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
606
607 return 1;
608}
609
610static unsigned long psu_afi_config(void)
611{
612 psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
613 psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
614 psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
615
616 return 1;
617}
618
619static unsigned long psu_ddr_phybringup_data(void)
620{
621 unsigned int regval = 0;
622
623 for (int tp = 0; tp < 20; tp++)
624 regval = Xil_In32(0xFD070018);
625 int cur_PLLCR0;
626
627 cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U;
628 int cur_DX8SL0PLLCR0;
629
630 cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U;
631 int cur_DX8SL1PLLCR0;
632
633 cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U;
634 int cur_DX8SL2PLLCR0;
635
636 cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U;
637 int cur_DX8SL3PLLCR0;
638
639 cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U;
640 int cur_DX8SL4PLLCR0;
641
642 cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U;
643 int cur_DX8SLBPLLCR0;
644
645 cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U;
646 Xil_Out32(0xFD080068, 0x02120000);
647 Xil_Out32(0xFD081404, 0x02120000);
648 Xil_Out32(0xFD081444, 0x02120000);
649 Xil_Out32(0xFD081484, 0x02120000);
650 Xil_Out32(0xFD0814C4, 0x02120000);
651 Xil_Out32(0xFD081504, 0x02120000);
652 Xil_Out32(0xFD0817C4, 0x02120000);
653 int cur_div2;
654
655 cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U;
656 int cur_fbdiv;
657
658 cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U;
659 dpll_prog(1, 49, 63, 625, 3, 3, 2);
660 for (int tp = 0; tp < 20; tp++)
661 regval = Xil_In32(0xFD070018);
662 unsigned int pll_retry = 10;
663 unsigned int pll_locked = 0;
664
665 while ((pll_retry > 0) && (!pll_locked)) {
666 Xil_Out32(0xFD080004, 0x00040010);
667 Xil_Out32(0xFD080004, 0x00040011);
668
669 while ((Xil_In32(0xFD080030) & 0x1) != 1)
670 ;
671 pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
672 >> 31;
673 pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
674 >> 16;
675 pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
676 pll_retry--;
677 }
678 Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
679 if (!pll_locked)
680 return 0;
681
682 Xil_Out32(0xFD080004U, 0x00040063U);
683 Xil_Out32(0xFD0800C0U, 0x00000001U);
684
685 while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
686 ;
687 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
688
689 while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
690 ;
691 Xil_Out32(0xFD070010U, 0x80000018U);
692 Xil_Out32(0xFD0701B0U, 0x00000005U);
693 regval = Xil_In32(0xFD070018);
694 while ((regval & 0x1) != 0x0)
695 regval = Xil_In32(0xFD070018);
696
697 regval = Xil_In32(0xFD070018);
698 regval = Xil_In32(0xFD070018);
699 regval = Xil_In32(0xFD070018);
700 regval = Xil_In32(0xFD070018);
701 regval = Xil_In32(0xFD070018);
702 regval = Xil_In32(0xFD070018);
703 regval = Xil_In32(0xFD070018);
704 regval = Xil_In32(0xFD070018);
705 regval = Xil_In32(0xFD070018);
706 regval = Xil_In32(0xFD070018);
707 Xil_Out32(0xFD070014U, 0x00000331U);
708 Xil_Out32(0xFD070010U, 0x80000018U);
709 regval = Xil_In32(0xFD070018);
710 while ((regval & 0x1) != 0x0)
711 regval = Xil_In32(0xFD070018);
712
713 regval = Xil_In32(0xFD070018);
714 regval = Xil_In32(0xFD070018);
715 regval = Xil_In32(0xFD070018);
716 regval = Xil_In32(0xFD070018);
717 regval = Xil_In32(0xFD070018);
718 regval = Xil_In32(0xFD070018);
719 regval = Xil_In32(0xFD070018);
720 regval = Xil_In32(0xFD070018);
721 regval = Xil_In32(0xFD070018);
722 regval = Xil_In32(0xFD070018);
723 Xil_Out32(0xFD070014U, 0x00000B36U);
724 Xil_Out32(0xFD070010U, 0x80000018U);
725 regval = Xil_In32(0xFD070018);
726 while ((regval & 0x1) != 0x0)
727 regval = Xil_In32(0xFD070018);
728
729 regval = Xil_In32(0xFD070018);
730 regval = Xil_In32(0xFD070018);
731 regval = Xil_In32(0xFD070018);
732 regval = Xil_In32(0xFD070018);
733 regval = Xil_In32(0xFD070018);
734 regval = Xil_In32(0xFD070018);
735 regval = Xil_In32(0xFD070018);
736 regval = Xil_In32(0xFD070018);
737 regval = Xil_In32(0xFD070018);
738 regval = Xil_In32(0xFD070018);
739 Xil_Out32(0xFD070014U, 0x00000C56U);
740 Xil_Out32(0xFD070010U, 0x80000018U);
741 regval = Xil_In32(0xFD070018);
742 while ((regval & 0x1) != 0x0)
743 regval = Xil_In32(0xFD070018);
744
745 regval = Xil_In32(0xFD070018);
746 regval = Xil_In32(0xFD070018);
747 regval = Xil_In32(0xFD070018);
748 regval = Xil_In32(0xFD070018);
749 regval = Xil_In32(0xFD070018);
750 regval = Xil_In32(0xFD070018);
751 regval = Xil_In32(0xFD070018);
752 regval = Xil_In32(0xFD070018);
753 regval = Xil_In32(0xFD070018);
754 regval = Xil_In32(0xFD070018);
755 Xil_Out32(0xFD070014U, 0x00000E19U);
756 Xil_Out32(0xFD070010U, 0x80000018U);
757 regval = Xil_In32(0xFD070018);
758 while ((regval & 0x1) != 0x0)
759 regval = Xil_In32(0xFD070018);
760
761 regval = Xil_In32(0xFD070018);
762 regval = Xil_In32(0xFD070018);
763 regval = Xil_In32(0xFD070018);
764 regval = Xil_In32(0xFD070018);
765 regval = Xil_In32(0xFD070018);
766 regval = Xil_In32(0xFD070018);
767 regval = Xil_In32(0xFD070018);
768 regval = Xil_In32(0xFD070018);
769 regval = Xil_In32(0xFD070018);
770 regval = Xil_In32(0xFD070018);
771 Xil_Out32(0xFD070014U, 0x00001616U);
772 Xil_Out32(0xFD070010U, 0x80000018U);
773 Xil_Out32(0xFD070010U, 0x80000010U);
774 Xil_Out32(0xFD0701B0U, 0x00000005U);
775 Xil_Out32(0xFD070320U, 0x00000001U);
776 while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
777 ;
778 prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U);
779 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
780 prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
781 prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U);
782 prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
783 prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
784 prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U);
785 prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
786 for (int tp = 0; tp < 20; tp++)
787 regval = Xil_In32(0xFD070018);
788
789 Xil_Out32(0xFD080068, cur_PLLCR0);
790 Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0);
791 Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0);
792 Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0);
793 Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0);
794 Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0);
795 Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0);
796 for (int tp = 0; tp < 20; tp++)
797 regval = Xil_In32(0xFD070018);
798
799 dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2);
800 for (int tp = 0; tp < 2000; tp++)
801 regval = Xil_In32(0xFD070018);
802
803 prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U);
804 prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U);
805 prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U);
806 prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U);
807 prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U);
808 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
809
810 while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
811 ;
812 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
813
814 while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
815 ;
816 for (int tp = 0; tp < 2000; tp++)
817 regval = Xil_In32(0xFD070018);
818
819 prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U);
820 prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
821 prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
822 prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U);
823 prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
824 for (int tp = 0; tp < 2000; tp++)
825 regval = Xil_In32(0xFD070018);
826
827 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
828 Xil_Out32(0xFD080004, 0x0014FE01);
829
830 regval = Xil_In32(0xFD080030);
831 while (regval != 0x8000007E)
832 regval = Xil_In32(0xFD080030);
833
834 Xil_Out32(0xFD080200U, 0x000091C7U);
835 regval = Xil_In32(0xFD080030);
836 while (regval != 0x80008FFF)
837 regval = Xil_In32(0xFD080030);
838
839 Xil_Out32(0xFD080200U, 0x800091C7U);
840 regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
841 if (regval != 0)
842 return 0;
843 prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
844 prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
845 prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
846 prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
847 Xil_Out32(0xFD070180U, 0x02160010U);
848 Xil_Out32(0xFD070060U, 0x00000000U);
849 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
850 for (int tp = 0; tp < 4000; tp++)
851 regval = Xil_In32(0xFD070018);
852
853 prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U);
854 prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U);
855 prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U);
856 prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U);
857 prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U);
858 prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U);
859 prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U);
860 prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U);
861 prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U);
862 prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U);
863 prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U);
864 prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U);
865 prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U);
866 prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U);
867 prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U);
868 prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U);
869 prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
870 prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
871 prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
872 prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
873 prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
874 prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
875 prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U);
876 prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU);
877 prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U);
878
879 return 1;
880}
881
882static int serdes_rst_seq(u32 pllsel, u32 lane3_protocol, u32 lane3_rate,
883 u32 lane2_protocol, u32 lane2_rate,
884 u32 lane1_protocol, u32 lane1_rate,
885 u32 lane0_protocol, u32 lane0_rate)
886{
887 Xil_Out32(0xFD410098, 0x00000000);
888 Xil_Out32(0xFD401010, 0x00000040);
889 Xil_Out32(0xFD405010, 0x00000040);
890 Xil_Out32(0xFD409010, 0x00000040);
891 Xil_Out32(0xFD40D010, 0x00000040);
892 Xil_Out32(0xFD402084, 0x00000080);
893 Xil_Out32(0xFD406084, 0x00000080);
894 Xil_Out32(0xFD40A084, 0x00000080);
895 Xil_Out32(0xFD40E084, 0x00000080);
896 Xil_Out32(0xFD410098, 0x00000004);
897 mask_delay(50);
898 if (lane0_rate == 1)
899 Xil_Out32(0xFD410098, 0x0000000E);
900 Xil_Out32(0xFD410098, 0x00000006);
901 if (lane0_rate == 1) {
902 Xil_Out32(0xFD40000C, 0x00000004);
903 Xil_Out32(0xFD40400C, 0x00000004);
904 Xil_Out32(0xFD40800C, 0x00000004);
905 Xil_Out32(0xFD40C00C, 0x00000004);
906 Xil_Out32(0xFD410098, 0x00000007);
907 mask_delay(400);
908 Xil_Out32(0xFD40000C, 0x0000000C);
909 Xil_Out32(0xFD40400C, 0x0000000C);
910 Xil_Out32(0xFD40800C, 0x0000000C);
911 Xil_Out32(0xFD40C00C, 0x0000000C);
912 mask_delay(15);
913 Xil_Out32(0xFD410098, 0x0000000F);
914 mask_delay(100);
915 }
916 if (pllsel == 0)
917 mask_poll(0xFD4023E4, 0x00000010U);
918 if (pllsel == 1)
919 mask_poll(0xFD4063E4, 0x00000010U);
920 if (pllsel == 2)
921 mask_poll(0xFD40A3E4, 0x00000010U);
922 if (pllsel == 3)
923 mask_poll(0xFD40E3E4, 0x00000010U);
924 mask_delay(50);
925 Xil_Out32(0xFD401010, 0x000000C0);
926 Xil_Out32(0xFD405010, 0x000000C0);
927 Xil_Out32(0xFD409010, 0x000000C0);
928 Xil_Out32(0xFD40D010, 0x000000C0);
929 Xil_Out32(0xFD401010, 0x00000080);
930 Xil_Out32(0xFD405010, 0x00000080);
931 Xil_Out32(0xFD409010, 0x00000080);
932 Xil_Out32(0xFD40D010, 0x00000080);
933
934 Xil_Out32(0xFD402084, 0x000000C0);
935 Xil_Out32(0xFD406084, 0x000000C0);
936 Xil_Out32(0xFD40A084, 0x000000C0);
937 Xil_Out32(0xFD40E084, 0x000000C0);
938 mask_delay(50);
939 Xil_Out32(0xFD402084, 0x00000080);
940 Xil_Out32(0xFD406084, 0x00000080);
941 Xil_Out32(0xFD40A084, 0x00000080);
942 Xil_Out32(0xFD40E084, 0x00000080);
943 mask_delay(50);
944 Xil_Out32(0xFD401010, 0x00000000);
945 Xil_Out32(0xFD405010, 0x00000000);
946 Xil_Out32(0xFD409010, 0x00000000);
947 Xil_Out32(0xFD40D010, 0x00000000);
948 Xil_Out32(0xFD402084, 0x00000000);
949 Xil_Out32(0xFD406084, 0x00000000);
950 Xil_Out32(0xFD40A084, 0x00000000);
951 Xil_Out32(0xFD40E084, 0x00000000);
952 mask_delay(500);
953 return 1;
954}
955
956static int serdes_bist_static_settings(u32 lane_active)
957{
958 if (lane_active == 0) {
959 Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
960 Xil_Out32(0xFD403068, 0x1);
961 Xil_Out32(0xFD40306C, 0x1);
962 Xil_Out32(0xFD4010AC, 0x0020);
963 Xil_Out32(0xFD403008, 0x0);
964 Xil_Out32(0xFD40300C, 0xF4);
965 Xil_Out32(0xFD403010, 0x0);
966 Xil_Out32(0xFD403014, 0x0);
967 Xil_Out32(0xFD403018, 0x00);
968 Xil_Out32(0xFD40301C, 0xFB);
969 Xil_Out32(0xFD403020, 0xFF);
970 Xil_Out32(0xFD403024, 0x0);
971 Xil_Out32(0xFD403028, 0x00);
972 Xil_Out32(0xFD40302C, 0x00);
973 Xil_Out32(0xFD403030, 0x4A);
974 Xil_Out32(0xFD403034, 0x4A);
975 Xil_Out32(0xFD403038, 0x4A);
976 Xil_Out32(0xFD40303C, 0x4A);
977 Xil_Out32(0xFD403040, 0x0);
978 Xil_Out32(0xFD403044, 0x14);
979 Xil_Out32(0xFD403048, 0x02);
980 Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
981 }
982 if (lane_active == 1) {
983 Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
984 Xil_Out32(0xFD407068, 0x1);
985 Xil_Out32(0xFD40706C, 0x1);
986 Xil_Out32(0xFD4050AC, 0x0020);
987 Xil_Out32(0xFD407008, 0x0);
988 Xil_Out32(0xFD40700C, 0xF4);
989 Xil_Out32(0xFD407010, 0x0);
990 Xil_Out32(0xFD407014, 0x0);
991 Xil_Out32(0xFD407018, 0x00);
992 Xil_Out32(0xFD40701C, 0xFB);
993 Xil_Out32(0xFD407020, 0xFF);
994 Xil_Out32(0xFD407024, 0x0);
995 Xil_Out32(0xFD407028, 0x00);
996 Xil_Out32(0xFD40702C, 0x00);
997 Xil_Out32(0xFD407030, 0x4A);
998 Xil_Out32(0xFD407034, 0x4A);
999 Xil_Out32(0xFD407038, 0x4A);
1000 Xil_Out32(0xFD40703C, 0x4A);
1001 Xil_Out32(0xFD407040, 0x0);
1002 Xil_Out32(0xFD407044, 0x14);
1003 Xil_Out32(0xFD407048, 0x02);
1004 Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
1005 }
1006
1007 if (lane_active == 2) {
1008 Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
1009 Xil_Out32(0xFD40B068, 0x1);
1010 Xil_Out32(0xFD40B06C, 0x1);
1011 Xil_Out32(0xFD4090AC, 0x0020);
1012 Xil_Out32(0xFD40B008, 0x0);
1013 Xil_Out32(0xFD40B00C, 0xF4);
1014 Xil_Out32(0xFD40B010, 0x0);
1015 Xil_Out32(0xFD40B014, 0x0);
1016 Xil_Out32(0xFD40B018, 0x00);
1017 Xil_Out32(0xFD40B01C, 0xFB);
1018 Xil_Out32(0xFD40B020, 0xFF);
1019 Xil_Out32(0xFD40B024, 0x0);
1020 Xil_Out32(0xFD40B028, 0x00);
1021 Xil_Out32(0xFD40B02C, 0x00);
1022 Xil_Out32(0xFD40B030, 0x4A);
1023 Xil_Out32(0xFD40B034, 0x4A);
1024 Xil_Out32(0xFD40B038, 0x4A);
1025 Xil_Out32(0xFD40B03C, 0x4A);
1026 Xil_Out32(0xFD40B040, 0x0);
1027 Xil_Out32(0xFD40B044, 0x14);
1028 Xil_Out32(0xFD40B048, 0x02);
1029 Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
1030 }
1031
1032 if (lane_active == 3) {
1033 Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
1034 Xil_Out32(0xFD40F068, 0x1);
1035 Xil_Out32(0xFD40F06C, 0x1);
1036 Xil_Out32(0xFD40D0AC, 0x0020);
1037 Xil_Out32(0xFD40F008, 0x0);
1038 Xil_Out32(0xFD40F00C, 0xF4);
1039 Xil_Out32(0xFD40F010, 0x0);
1040 Xil_Out32(0xFD40F014, 0x0);
1041 Xil_Out32(0xFD40F018, 0x00);
1042 Xil_Out32(0xFD40F01C, 0xFB);
1043 Xil_Out32(0xFD40F020, 0xFF);
1044 Xil_Out32(0xFD40F024, 0x0);
1045 Xil_Out32(0xFD40F028, 0x00);
1046 Xil_Out32(0xFD40F02C, 0x00);
1047 Xil_Out32(0xFD40F030, 0x4A);
1048 Xil_Out32(0xFD40F034, 0x4A);
1049 Xil_Out32(0xFD40F038, 0x4A);
1050 Xil_Out32(0xFD40F03C, 0x4A);
1051 Xil_Out32(0xFD40F040, 0x0);
1052 Xil_Out32(0xFD40F044, 0x14);
1053 Xil_Out32(0xFD40F048, 0x02);
1054 Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
1055 }
1056 return 1;
1057}
1058
1059static int serdes_bist_run(u32 lane_active)
1060{
1061 if (lane_active == 0) {
1062 psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
1063 psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
1064 psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U);
1065 Xil_Out32(0xFD4010AC, 0x0020);
1066 Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1));
1067 }
1068 if (lane_active == 1) {
1069 psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U);
1070 psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U);
1071 psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U);
1072 Xil_Out32(0xFD4050AC, 0x0020);
1073 Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1));
1074 }
1075 if (lane_active == 2) {
1076 psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U);
1077 psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U);
1078 psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U);
1079 Xil_Out32(0xFD4090AC, 0x0020);
1080 Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1));
1081 }
1082 if (lane_active == 3) {
1083 psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U);
1084 psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U);
1085 psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U);
1086 Xil_Out32(0xFD40D0AC, 0x0020);
1087 Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1));
1088 }
1089 mask_delay(100);
1090 return 1;
1091}
1092
1093static int serdes_bist_result(u32 lane_active)
1094{
1095 u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0;
1096
1097 if (lane_active == 0) {
1098 pkt_cnt_l0 = Xil_In32(0xFD40304C);
1099 pkt_cnt_h0 = Xil_In32(0xFD403050);
1100 err_cnt_l0 = Xil_In32(0xFD403054);
1101 err_cnt_h0 = Xil_In32(0xFD403058);
1102 }
1103 if (lane_active == 1) {
1104 pkt_cnt_l0 = Xil_In32(0xFD40704C);
1105 pkt_cnt_h0 = Xil_In32(0xFD407050);
1106 err_cnt_l0 = Xil_In32(0xFD407054);
1107 err_cnt_h0 = Xil_In32(0xFD407058);
1108 }
1109 if (lane_active == 2) {
1110 pkt_cnt_l0 = Xil_In32(0xFD40B04C);
1111 pkt_cnt_h0 = Xil_In32(0xFD40B050);
1112 err_cnt_l0 = Xil_In32(0xFD40B054);
1113 err_cnt_h0 = Xil_In32(0xFD40B058);
1114 }
1115 if (lane_active == 3) {
1116 pkt_cnt_l0 = Xil_In32(0xFD40F04C);
1117 pkt_cnt_h0 = Xil_In32(0xFD40F050);
1118 err_cnt_l0 = Xil_In32(0xFD40F054);
1119 err_cnt_h0 = Xil_In32(0xFD40F058);
1120 }
1121 if (lane_active == 0)
1122 Xil_Out32(0xFD403004, 0x0);
1123 if (lane_active == 1)
1124 Xil_Out32(0xFD407004, 0x0);
1125 if (lane_active == 2)
1126 Xil_Out32(0xFD40B004, 0x0);
1127 if (lane_active == 3)
1128 Xil_Out32(0xFD40F004, 0x0);
1129 if (err_cnt_l0 > 0 || err_cnt_h0 > 0 ||
1130 (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0))
1131 return 0;
1132 return 1;
1133}
1134
1135static int serdes_illcalib_pcie_gen1(u32 pllsel, u32 lane3_protocol,
1136 u32 lane3_rate, u32 lane2_protocol,
1137 u32 lane2_rate, u32 lane1_protocol,
1138 u32 lane1_rate, u32 lane0_protocol,
1139 u32 lane0_rate, u32 gen2_calib)
1140{
1141 u64 tempbistresult;
1142 u32 currbistresult[4];
1143 u32 prevbistresult[4];
1144 u32 itercount = 0;
1145 u32 ill12_val[4], ill1_val[4];
1146 u32 loop = 0;
1147 u32 iterresult[8];
1148 u32 meancount[4];
1149 u32 bistpasscount[4];
1150 u32 meancountalt[4];
1151 u32 meancountalt_bistpasscount[4];
1152 u32 lane0_active;
1153 u32 lane1_active;
1154 u32 lane2_active;
1155 u32 lane3_active;
1156
1157 lane0_active = (lane0_protocol == 1);
1158 lane1_active = (lane1_protocol == 1);
1159 lane2_active = (lane2_protocol == 1);
1160 lane3_active = (lane3_protocol == 1);
1161 for (loop = 0; loop <= 3; loop++) {
1162 iterresult[loop] = 0;
1163 iterresult[loop + 4] = 0;
1164 meancountalt[loop] = 0;
1165 meancountalt_bistpasscount[loop] = 0;
1166 meancount[loop] = 0;
1167 prevbistresult[loop] = 0;
1168 bistpasscount[loop] = 0;
1169 }
1170 itercount = 0;
1171 if (lane0_active)
1172 serdes_bist_static_settings(0);
1173 if (lane1_active)
1174 serdes_bist_static_settings(1);
1175 if (lane2_active)
1176 serdes_bist_static_settings(2);
1177 if (lane3_active)
1178 serdes_bist_static_settings(3);
1179 do {
1180 if (gen2_calib != 1) {
1181 if (lane0_active == 1)
1182 ill1_val[0] = ((0x04 + itercount * 8) % 0x100);
1183 if (lane0_active == 1)
1184 ill12_val[0] =
1185 ((0x04 + itercount * 8) >=
1186 0x100) ? 0x10 : 0x00;
1187 if (lane1_active == 1)
1188 ill1_val[1] = ((0x04 + itercount * 8) % 0x100);
1189 if (lane1_active == 1)
1190 ill12_val[1] =
1191 ((0x04 + itercount * 8) >=
1192 0x100) ? 0x10 : 0x00;
1193 if (lane2_active == 1)
1194 ill1_val[2] = ((0x04 + itercount * 8) % 0x100);
1195 if (lane2_active == 1)
1196 ill12_val[2] =
1197 ((0x04 + itercount * 8) >=
1198 0x100) ? 0x10 : 0x00;
1199 if (lane3_active == 1)
1200 ill1_val[3] = ((0x04 + itercount * 8) % 0x100);
1201 if (lane3_active == 1)
1202 ill12_val[3] =
1203 ((0x04 + itercount * 8) >=
1204 0x100) ? 0x10 : 0x00;
1205
1206 if (lane0_active == 1)
1207 Xil_Out32(0xFD401924, ill1_val[0]);
1208 if (lane0_active == 1)
1209 psu_mask_write(0xFD401990, 0x000000F0U,
1210 ill12_val[0]);
1211 if (lane1_active == 1)
1212 Xil_Out32(0xFD405924, ill1_val[1]);
1213 if (lane1_active == 1)
1214 psu_mask_write(0xFD405990, 0x000000F0U,
1215 ill12_val[1]);
1216 if (lane2_active == 1)
1217 Xil_Out32(0xFD409924, ill1_val[2]);
1218 if (lane2_active == 1)
1219 psu_mask_write(0xFD409990, 0x000000F0U,
1220 ill12_val[2]);
1221 if (lane3_active == 1)
1222 Xil_Out32(0xFD40D924, ill1_val[3]);
1223 if (lane3_active == 1)
1224 psu_mask_write(0xFD40D990, 0x000000F0U,
1225 ill12_val[3]);
1226 }
1227 if (gen2_calib == 1) {
1228 if (lane0_active == 1)
1229 ill1_val[0] = ((0x104 + itercount * 8) % 0x100);
1230 if (lane0_active == 1)
1231 ill12_val[0] =
1232 ((0x104 + itercount * 8) >=
1233 0x200) ? 0x02 : 0x01;
1234 if (lane1_active == 1)
1235 ill1_val[1] = ((0x104 + itercount * 8) % 0x100);
1236 if (lane1_active == 1)
1237 ill12_val[1] =
1238 ((0x104 + itercount * 8) >=
1239 0x200) ? 0x02 : 0x01;
1240 if (lane2_active == 1)
1241 ill1_val[2] = ((0x104 + itercount * 8) % 0x100);
1242 if (lane2_active == 1)
1243 ill12_val[2] =
1244 ((0x104 + itercount * 8) >=
1245 0x200) ? 0x02 : 0x01;
1246 if (lane3_active == 1)
1247 ill1_val[3] = ((0x104 + itercount * 8) % 0x100);
1248 if (lane3_active == 1)
1249 ill12_val[3] =
1250 ((0x104 + itercount * 8) >=
1251 0x200) ? 0x02 : 0x01;
1252
1253 if (lane0_active == 1)
1254 Xil_Out32(0xFD401928, ill1_val[0]);
1255 if (lane0_active == 1)
1256 psu_mask_write(0xFD401990, 0x0000000FU,
1257 ill12_val[0]);
1258 if (lane1_active == 1)
1259 Xil_Out32(0xFD405928, ill1_val[1]);
1260 if (lane1_active == 1)
1261 psu_mask_write(0xFD405990, 0x0000000FU,
1262 ill12_val[1]);
1263 if (lane2_active == 1)
1264 Xil_Out32(0xFD409928, ill1_val[2]);
1265 if (lane2_active == 1)
1266 psu_mask_write(0xFD409990, 0x0000000FU,
1267 ill12_val[2]);
1268 if (lane3_active == 1)
1269 Xil_Out32(0xFD40D928, ill1_val[3]);
1270 if (lane3_active == 1)
1271 psu_mask_write(0xFD40D990, 0x0000000FU,
1272 ill12_val[3]);
1273 }
1274
1275 if (lane0_active == 1)
1276 psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U);
1277 if (lane1_active == 1)
1278 psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U);
1279 if (lane2_active == 1)
1280 psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U);
1281 if (lane3_active == 1)
1282 psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U);
1283 if (lane0_active == 1)
1284 currbistresult[0] = 0;
1285 if (lane1_active == 1)
1286 currbistresult[1] = 0;
1287 if (lane2_active == 1)
1288 currbistresult[2] = 0;
1289 if (lane3_active == 1)
1290 currbistresult[3] = 0;
1291 serdes_rst_seq(pllsel, lane3_protocol, lane3_rate,
1292 lane2_protocol, lane2_rate, lane1_protocol,
1293 lane1_rate, lane0_protocol, lane0_rate);
1294 if (lane3_active == 1)
1295 serdes_bist_run(3);
1296 if (lane2_active == 1)
1297 serdes_bist_run(2);
1298 if (lane1_active == 1)
1299 serdes_bist_run(1);
1300 if (lane0_active == 1)
1301 serdes_bist_run(0);
1302 tempbistresult = 0;
1303 if (lane3_active == 1)
1304 tempbistresult = tempbistresult | serdes_bist_result(3);
1305 tempbistresult = tempbistresult << 1;
1306 if (lane2_active == 1)
1307 tempbistresult = tempbistresult | serdes_bist_result(2);
1308 tempbistresult = tempbistresult << 1;
1309 if (lane1_active == 1)
1310 tempbistresult = tempbistresult | serdes_bist_result(1);
1311 tempbistresult = tempbistresult << 1;
1312 if (lane0_active == 1)
1313 tempbistresult = tempbistresult | serdes_bist_result(0);
1314 Xil_Out32(0xFD410098, 0x0);
1315 Xil_Out32(0xFD410098, 0x2);
1316
1317 if (itercount < 32) {
1318 iterresult[0] =
1319 ((iterresult[0] << 1) |
1320 ((tempbistresult & 0x1) == 0x1));
1321 iterresult[1] =
1322 ((iterresult[1] << 1) |
1323 ((tempbistresult & 0x2) == 0x2));
1324 iterresult[2] =
1325 ((iterresult[2] << 1) |
1326 ((tempbistresult & 0x4) == 0x4));
1327 iterresult[3] =
1328 ((iterresult[3] << 1) |
1329 ((tempbistresult & 0x8) == 0x8));
1330 } else {
1331 iterresult[4] =
1332 ((iterresult[4] << 1) |
1333 ((tempbistresult & 0x1) == 0x1));
1334 iterresult[5] =
1335 ((iterresult[5] << 1) |
1336 ((tempbistresult & 0x2) == 0x2));
1337 iterresult[6] =
1338 ((iterresult[6] << 1) |
1339 ((tempbistresult & 0x4) == 0x4));
1340 iterresult[7] =
1341 ((iterresult[7] << 1) |
1342 ((tempbistresult & 0x8) == 0x8));
1343 }
1344 currbistresult[0] =
1345 currbistresult[0] | ((tempbistresult & 0x1) == 1);
1346 currbistresult[1] =
1347 currbistresult[1] | ((tempbistresult & 0x2) == 0x2);
1348 currbistresult[2] =
1349 currbistresult[2] | ((tempbistresult & 0x4) == 0x4);
1350 currbistresult[3] =
1351 currbistresult[3] | ((tempbistresult & 0x8) == 0x8);
1352
1353 for (loop = 0; loop <= 3; loop++) {
1354 if (currbistresult[loop] == 1 &&
1355 prevbistresult[loop] == 1)
1356 bistpasscount[loop] = bistpasscount[loop] + 1;
1357 if (bistpasscount[loop] < 4 &&
1358 currbistresult[loop] == 0 && itercount > 2) {
1359 if (meancountalt_bistpasscount[loop] <
1360 bistpasscount[loop]) {
1361 meancountalt_bistpasscount[loop] =
1362 bistpasscount[loop];
1363 meancountalt[loop] =
1364 ((itercount - 1) -
1365 ((bistpasscount[loop] + 1) / 2));
1366 }
1367 bistpasscount[loop] = 0;
1368 }
1369 if (meancount[loop] == 0 && bistpasscount[loop] >= 4 &&
1370 (currbistresult[loop] == 0 || itercount == 63) &&
1371 prevbistresult[loop] == 1)
1372 meancount[loop] =
1373 itercount - 1 -
1374 ((bistpasscount[loop] + 1) / 2);
1375 prevbistresult[loop] = currbistresult[loop];
1376 }
1377 } while (++itercount < 64);
1378
1379 for (loop = 0; loop <= 3; loop++) {
1380 if (lane0_active == 0 && loop == 0)
1381 continue;
1382 if (lane1_active == 0 && loop == 1)
1383 continue;
1384 if (lane2_active == 0 && loop == 2)
1385 continue;
1386 if (lane3_active == 0 && loop == 3)
1387 continue;
1388
1389 if (meancount[loop] == 0)
1390 meancount[loop] = meancountalt[loop];
1391
1392 if (gen2_calib != 1) {
1393 ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100);
1394 ill12_val[loop] =
1395 ((0x04 + meancount[loop] * 8) >=
1396 0x100) ? 0x10 : 0x00;
1397 }
1398 if (gen2_calib == 1) {
1399 ill1_val[loop] =
1400 ((0x104 + meancount[loop] * 8) % 0x100);
1401 ill12_val[loop] =
1402 ((0x104 + meancount[loop] * 8) >=
1403 0x200) ? 0x02 : 0x01;
1404 }
1405 }
1406 if (gen2_calib != 1) {
1407 if (lane0_active == 1)
1408 Xil_Out32(0xFD401924, ill1_val[0]);
1409 if (lane0_active == 1)
1410 psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]);
1411 if (lane1_active == 1)
1412 Xil_Out32(0xFD405924, ill1_val[1]);
1413 if (lane1_active == 1)
1414 psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]);
1415 if (lane2_active == 1)
1416 Xil_Out32(0xFD409924, ill1_val[2]);
1417 if (lane2_active == 1)
1418 psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]);
1419 if (lane3_active == 1)
1420 Xil_Out32(0xFD40D924, ill1_val[3]);
1421 if (lane3_active == 1)
1422 psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]);
1423 }
1424 if (gen2_calib == 1) {
1425 if (lane0_active == 1)
1426 Xil_Out32(0xFD401928, ill1_val[0]);
1427 if (lane0_active == 1)
1428 psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]);
1429 if (lane1_active == 1)
1430 Xil_Out32(0xFD405928, ill1_val[1]);
1431 if (lane1_active == 1)
1432 psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]);
1433 if (lane2_active == 1)
1434 Xil_Out32(0xFD409928, ill1_val[2]);
1435 if (lane2_active == 1)
1436 psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]);
1437 if (lane3_active == 1)
1438 Xil_Out32(0xFD40D928, ill1_val[3]);
1439 if (lane3_active == 1)
1440 psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]);
1441 }
1442
1443 if (lane0_active == 1)
1444 psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U);
1445 if (lane1_active == 1)
1446 psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U);
1447 if (lane2_active == 1)
1448 psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U);
1449 if (lane3_active == 1)
1450 psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U);
1451
1452 Xil_Out32(0xFD410098, 0);
1453 if (lane0_active == 1) {
1454 Xil_Out32(0xFD403004, 0);
1455 Xil_Out32(0xFD403008, 0);
1456 Xil_Out32(0xFD40300C, 0);
1457 Xil_Out32(0xFD403010, 0);
1458 Xil_Out32(0xFD403014, 0);
1459 Xil_Out32(0xFD403018, 0);
1460 Xil_Out32(0xFD40301C, 0);
1461 Xil_Out32(0xFD403020, 0);
1462 Xil_Out32(0xFD403024, 0);
1463 Xil_Out32(0xFD403028, 0);
1464 Xil_Out32(0xFD40302C, 0);
1465 Xil_Out32(0xFD403030, 0);
1466 Xil_Out32(0xFD403034, 0);
1467 Xil_Out32(0xFD403038, 0);
1468 Xil_Out32(0xFD40303C, 0);
1469 Xil_Out32(0xFD403040, 0);
1470 Xil_Out32(0xFD403044, 0);
1471 Xil_Out32(0xFD403048, 0);
1472 Xil_Out32(0xFD40304C, 0);
1473 Xil_Out32(0xFD403050, 0);
1474 Xil_Out32(0xFD403054, 0);
1475 Xil_Out32(0xFD403058, 0);
1476 Xil_Out32(0xFD403068, 1);
1477 Xil_Out32(0xFD40306C, 0);
1478 Xil_Out32(0xFD4010AC, 0);
1479 psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U);
1480 psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U);
1481 psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U);
1482 }
1483 if (lane1_active == 1) {
1484 Xil_Out32(0xFD407004, 0);
1485 Xil_Out32(0xFD407008, 0);
1486 Xil_Out32(0xFD40700C, 0);
1487 Xil_Out32(0xFD407010, 0);
1488 Xil_Out32(0xFD407014, 0);
1489 Xil_Out32(0xFD407018, 0);
1490 Xil_Out32(0xFD40701C, 0);
1491 Xil_Out32(0xFD407020, 0);
1492 Xil_Out32(0xFD407024, 0);
1493 Xil_Out32(0xFD407028, 0);
1494 Xil_Out32(0xFD40702C, 0);
1495 Xil_Out32(0xFD407030, 0);
1496 Xil_Out32(0xFD407034, 0);
1497 Xil_Out32(0xFD407038, 0);
1498 Xil_Out32(0xFD40703C, 0);
1499 Xil_Out32(0xFD407040, 0);
1500 Xil_Out32(0xFD407044, 0);
1501 Xil_Out32(0xFD407048, 0);
1502 Xil_Out32(0xFD40704C, 0);
1503 Xil_Out32(0xFD407050, 0);
1504 Xil_Out32(0xFD407054, 0);
1505 Xil_Out32(0xFD407058, 0);
1506 Xil_Out32(0xFD407068, 1);
1507 Xil_Out32(0xFD40706C, 0);
1508 Xil_Out32(0xFD4050AC, 0);
1509 psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U);
1510 psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U);
1511 psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U);
1512 }
1513 if (lane2_active == 1) {
1514 Xil_Out32(0xFD40B004, 0);
1515 Xil_Out32(0xFD40B008, 0);
1516 Xil_Out32(0xFD40B00C, 0);
1517 Xil_Out32(0xFD40B010, 0);
1518 Xil_Out32(0xFD40B014, 0);
1519 Xil_Out32(0xFD40B018, 0);
1520 Xil_Out32(0xFD40B01C, 0);
1521 Xil_Out32(0xFD40B020, 0);
1522 Xil_Out32(0xFD40B024, 0);
1523 Xil_Out32(0xFD40B028, 0);
1524 Xil_Out32(0xFD40B02C, 0);
1525 Xil_Out32(0xFD40B030, 0);
1526 Xil_Out32(0xFD40B034, 0);
1527 Xil_Out32(0xFD40B038, 0);
1528 Xil_Out32(0xFD40B03C, 0);
1529 Xil_Out32(0xFD40B040, 0);
1530 Xil_Out32(0xFD40B044, 0);
1531 Xil_Out32(0xFD40B048, 0);
1532 Xil_Out32(0xFD40B04C, 0);
1533 Xil_Out32(0xFD40B050, 0);
1534 Xil_Out32(0xFD40B054, 0);
1535 Xil_Out32(0xFD40B058, 0);
1536 Xil_Out32(0xFD40B068, 1);
1537 Xil_Out32(0xFD40B06C, 0);
1538 Xil_Out32(0xFD4090AC, 0);
1539 psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U);
1540 psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U);
1541 psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U);
1542 }
1543 if (lane3_active == 1) {
1544 Xil_Out32(0xFD40F004, 0);
1545 Xil_Out32(0xFD40F008, 0);
1546 Xil_Out32(0xFD40F00C, 0);
1547 Xil_Out32(0xFD40F010, 0);
1548 Xil_Out32(0xFD40F014, 0);
1549 Xil_Out32(0xFD40F018, 0);
1550 Xil_Out32(0xFD40F01C, 0);
1551 Xil_Out32(0xFD40F020, 0);
1552 Xil_Out32(0xFD40F024, 0);
1553 Xil_Out32(0xFD40F028, 0);
1554 Xil_Out32(0xFD40F02C, 0);
1555 Xil_Out32(0xFD40F030, 0);
1556 Xil_Out32(0xFD40F034, 0);
1557 Xil_Out32(0xFD40F038, 0);
1558 Xil_Out32(0xFD40F03C, 0);
1559 Xil_Out32(0xFD40F040, 0);
1560 Xil_Out32(0xFD40F044, 0);
1561 Xil_Out32(0xFD40F048, 0);
1562 Xil_Out32(0xFD40F04C, 0);
1563 Xil_Out32(0xFD40F050, 0);
1564 Xil_Out32(0xFD40F054, 0);
1565 Xil_Out32(0xFD40F058, 0);
1566 Xil_Out32(0xFD40F068, 1);
1567 Xil_Out32(0xFD40F06C, 0);
1568 Xil_Out32(0xFD40D0AC, 0);
1569 psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U);
1570 psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U);
1571 psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U);
1572 }
1573 return 1;
1574}
1575
1576static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
1577 u32 lane2_protocol, u32 lane2_rate,
1578 u32 lane1_protocol, u32 lane1_rate,
1579 u32 lane0_protocol, u32 lane0_rate)
1580{
1581 unsigned int rdata = 0;
1582 unsigned int sata_gen2 = 1;
1583 unsigned int temp_ill12 = 0;
1584 unsigned int temp_PLL_REF_SEL_OFFSET;
1585 unsigned int temp_TM_IQ_ILL1;
1586 unsigned int temp_TM_E_ILL1;
1587 unsigned int temp_tx_dig_tm_61;
1588 unsigned int temp_tm_dig_6;
1589 unsigned int temp_pll_fbdiv_frac_3_msb_offset;
1590
1591 if (lane0_protocol == 2 || lane0_protocol == 1) {
1592 Xil_Out32(0xFD401910, 0xF3);
1593 Xil_Out32(0xFD40193C, 0xF3);
1594 Xil_Out32(0xFD401914, 0xF3);
1595 Xil_Out32(0xFD401940, 0xF3);
1596 }
1597 if (lane1_protocol == 2 || lane1_protocol == 1) {
1598 Xil_Out32(0xFD405910, 0xF3);
1599 Xil_Out32(0xFD40593C, 0xF3);
1600 Xil_Out32(0xFD405914, 0xF3);
1601 Xil_Out32(0xFD405940, 0xF3);
1602 }
1603 if (lane2_protocol == 2 || lane2_protocol == 1) {
1604 Xil_Out32(0xFD409910, 0xF3);
1605 Xil_Out32(0xFD40993C, 0xF3);
1606 Xil_Out32(0xFD409914, 0xF3);
1607 Xil_Out32(0xFD409940, 0xF3);
1608 }
1609 if (lane3_protocol == 2 || lane3_protocol == 1) {
1610 Xil_Out32(0xFD40D910, 0xF3);
1611 Xil_Out32(0xFD40D93C, 0xF3);
1612 Xil_Out32(0xFD40D914, 0xF3);
1613 Xil_Out32(0xFD40D940, 0xF3);
1614 }
1615
1616 if (sata_gen2 == 1) {
1617 if (lane0_protocol == 2) {
1618 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360);
1619 Xil_Out32(0xFD402360, 0x0);
1620 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000);
1621 psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
1622 temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8);
1623 temp_TM_E_ILL1 = Xil_In32(0xFD401924);
1624 Xil_Out32(0xFD4018F8, 0x78);
1625 temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4);
1626 temp_tm_dig_6 = Xil_In32(0xFD40106C);
1627 psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U);
1628 psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U);
1629 temp_ill12 = Xil_In32(0xFD401990) & 0xF0;
1630
1631 serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 0, 1, 0, 0);
1632
1633 Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset);
1634 Xil_Out32(0xFD410000, temp_PLL_REF_SEL_OFFSET);
1635 Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1);
1636 Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61);
1637 Xil_Out32(0xFD40106C, temp_tm_dig_6);
1638 Xil_Out32(0xFD401928, Xil_In32(0xFD401924));
1639 temp_ill12 =
1640 temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF);
1641 Xil_Out32(0xFD401990, temp_ill12);
1642 Xil_Out32(0xFD401924, temp_TM_E_ILL1);
1643 }
1644 if (lane1_protocol == 2) {
1645 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360);
1646 Xil_Out32(0xFD406360, 0x0);
1647 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004);
1648 psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
1649 temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8);
1650 temp_TM_E_ILL1 = Xil_In32(0xFD405924);
1651 Xil_Out32(0xFD4058F8, 0x78);
1652 temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4);
1653 temp_tm_dig_6 = Xil_In32(0xFD40506C);
1654 psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U);
1655 psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U);
1656 temp_ill12 = Xil_In32(0xFD405990) & 0xF0;
1657
1658 serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 1, 0, 0, 0, 0);
1659
1660 Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset);
1661 Xil_Out32(0xFD410004, temp_PLL_REF_SEL_OFFSET);
1662 Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1);
1663 Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61);
1664 Xil_Out32(0xFD40506C, temp_tm_dig_6);
1665 Xil_Out32(0xFD405928, Xil_In32(0xFD405924));
1666 temp_ill12 =
1667 temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF);
1668 Xil_Out32(0xFD405990, temp_ill12);
1669 Xil_Out32(0xFD405924, temp_TM_E_ILL1);
1670 }
1671 if (lane2_protocol == 2) {
1672 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360);
1673 Xil_Out32(0xFD40A360, 0x0);
1674 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008);
1675 psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU);
1676 temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8);
1677 temp_TM_E_ILL1 = Xil_In32(0xFD409924);
1678 Xil_Out32(0xFD4098F8, 0x78);
1679 temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4);
1680 temp_tm_dig_6 = Xil_In32(0xFD40906C);
1681 psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U);
1682 psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U);
1683 temp_ill12 = Xil_In32(0xFD409990) & 0xF0;
1684
1685 serdes_illcalib_pcie_gen1(2, 0, 0, 1, 0, 0, 0, 0, 0, 0);
1686
1687 Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset);
1688 Xil_Out32(0xFD410008, temp_PLL_REF_SEL_OFFSET);
1689 Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1);
1690 Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61);
1691 Xil_Out32(0xFD40906C, temp_tm_dig_6);
1692 Xil_Out32(0xFD409928, Xil_In32(0xFD409924));
1693 temp_ill12 =
1694 temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF);
1695 Xil_Out32(0xFD409990, temp_ill12);
1696 Xil_Out32(0xFD409924, temp_TM_E_ILL1);
1697 }
1698 if (lane3_protocol == 2) {
1699 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360);
1700 Xil_Out32(0xFD40E360, 0x0);
1701 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C);
1702 psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU);
1703 temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8);
1704 temp_TM_E_ILL1 = Xil_In32(0xFD40D924);
1705 Xil_Out32(0xFD40D8F8, 0x78);
1706 temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4);
1707 temp_tm_dig_6 = Xil_In32(0xFD40D06C);
1708 psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U);
1709 psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U);
1710 temp_ill12 = Xil_In32(0xFD40D990) & 0xF0;
1711
1712 serdes_illcalib_pcie_gen1(3, 1, 0, 0, 0, 0, 0, 0, 0, 0);
1713
1714 Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset);
1715 Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
1716 Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1);
1717 Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61);
1718 Xil_Out32(0xFD40D06C, temp_tm_dig_6);
1719 Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924));
1720 temp_ill12 =
1721 temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF);
1722 Xil_Out32(0xFD40D990, temp_ill12);
1723 Xil_Out32(0xFD40D924, temp_TM_E_ILL1);
1724 }
1725 rdata = Xil_In32(0xFD410098);
1726 rdata = (rdata & 0xDF);
1727 Xil_Out32(0xFD410098, rdata);
1728 }
1729
1730 if (lane0_protocol == 2 && lane0_rate == 3) {
1731 psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
1732 psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U);
1733 }
1734 if (lane1_protocol == 2 && lane1_rate == 3) {
1735 psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U);
1736 psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U);
1737 }
1738 if (lane2_protocol == 2 && lane2_rate == 3) {
1739 psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U);
1740 psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U);
1741 }
1742 if (lane3_protocol == 2 && lane3_rate == 3) {
1743 psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
1744 psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U);
1745 }
1746
1747 if (lane0_protocol == 1) {
1748 if (lane0_rate == 0) {
1749 serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate,
1750 lane2_protocol, lane2_rate,
1751 lane1_protocol, lane1_rate,
1752 lane0_protocol, 0, 0);
1753 } else {
1754 serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate,
1755 lane2_protocol, lane2_rate,
1756 lane1_protocol, lane1_rate,
1757 lane0_protocol, 0, 0);
1758 serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate,
1759 lane2_protocol, lane2_rate,
1760 lane1_protocol, lane1_rate,
1761 lane0_protocol, lane0_rate,
1762 1);
1763 }
1764 }
1765
1766 if (lane0_protocol == 3)
1767 Xil_Out32(0xFD401914, 0xF3);
1768 if (lane0_protocol == 3)
1769 Xil_Out32(0xFD401940, 0xF3);
1770 if (lane0_protocol == 3)
1771 Xil_Out32(0xFD401990, 0x20);
1772 if (lane0_protocol == 3)
1773 Xil_Out32(0xFD401924, 0x37);
1774
1775 if (lane1_protocol == 3)
1776 Xil_Out32(0xFD405914, 0xF3);
1777 if (lane1_protocol == 3)
1778 Xil_Out32(0xFD405940, 0xF3);
1779 if (lane1_protocol == 3)
1780 Xil_Out32(0xFD405990, 0x20);
1781 if (lane1_protocol == 3)
1782 Xil_Out32(0xFD405924, 0x37);
1783
1784 if (lane2_protocol == 3)
1785 Xil_Out32(0xFD409914, 0xF3);
1786 if (lane2_protocol == 3)
1787 Xil_Out32(0xFD409940, 0xF3);
1788 if (lane2_protocol == 3)
1789 Xil_Out32(0xFD409990, 0x20);
1790 if (lane2_protocol == 3)
1791 Xil_Out32(0xFD409924, 0x37);
1792
1793 if (lane3_protocol == 3)
1794 Xil_Out32(0xFD40D914, 0xF3);
1795 if (lane3_protocol == 3)
1796 Xil_Out32(0xFD40D940, 0xF3);
1797 if (lane3_protocol == 3)
1798 Xil_Out32(0xFD40D990, 0x20);
1799 if (lane3_protocol == 3)
1800 Xil_Out32(0xFD40D924, 0x37);
1801
1802 return 1;
1803}
1804
1805static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly,
1806 int d_lock_cnt, int d_lfhf, int d_cp, int d_res)
1807{
1808 unsigned int pll_ctrl_regval;
1809 unsigned int pll_status_regval;
1810
1811 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
1812 pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U);
1813 pll_ctrl_regval = pll_ctrl_regval | (div2 << 16);
1814 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
1815
1816 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
1817 pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U);
1818 pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25);
1819 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
1820
1821 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
1822 pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U);
1823 pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13);
1824 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
1825
1826 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
1827 pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U);
1828 pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10);
1829 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
1830
1831 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
1832 pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U);
1833 pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5);
1834 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
1835
1836 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
1837 pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU);
1838 pll_ctrl_regval = pll_ctrl_regval | (d_res << 0);
1839 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
1840
1841 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
1842 pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U);
1843 pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8);
1844 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
1845
1846 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
1847 pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
1848 pll_ctrl_regval = pll_ctrl_regval | (1 << 3);
1849 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
1850
1851 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
1852 pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
1853 pll_ctrl_regval = pll_ctrl_regval | (1 << 0);
1854 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
1855
1856 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
1857 pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
1858 pll_ctrl_regval = pll_ctrl_regval | (0 << 0);
1859 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
1860
1861 pll_status_regval = 0x00000000;
1862 while ((pll_status_regval & 0x00000002U) != 0x00000002U)
1863 pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044));
1864
1865 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
1866 pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
1867 pll_ctrl_regval = pll_ctrl_regval | (0 << 3);
1868 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
1869}
1870
1871static int serdes_enb_coarse_saturation(void)
1872{
1873 Xil_Out32(0xFD402094, 0x00000010);
1874 Xil_Out32(0xFD406094, 0x00000010);
1875 Xil_Out32(0xFD40A094, 0x00000010);
1876 Xil_Out32(0xFD40E094, 0x00000010);
1877 return 1;
1878}
1879
1880static int serdes_fixcal_code(void)
1881{
1882 int maskstatus = 1;
1883 unsigned int rdata = 0;
1884 unsigned int match_pmos_code[23];
1885 unsigned int match_nmos_code[23];
1886 unsigned int match_ical_code[7];
1887 unsigned int match_rcal_code[7];
1888 unsigned int p_code = 0;
1889 unsigned int n_code = 0;
1890 unsigned int i_code = 0;
1891 unsigned int r_code = 0;
1892 unsigned int repeat_count = 0;
1893 unsigned int L3_TM_CALIB_DIG20 = 0;
1894 unsigned int L3_TM_CALIB_DIG19 = 0;
1895 unsigned int L3_TM_CALIB_DIG18 = 0;
1896 unsigned int L3_TM_CALIB_DIG16 = 0;
1897 unsigned int L3_TM_CALIB_DIG15 = 0;
1898 unsigned int L3_TM_CALIB_DIG14 = 0;
1899 int i = 0;
1900 int count = 0;
1901
1902 rdata = Xil_In32(0xFD40289C);
1903 rdata = rdata & ~0x03;
1904 rdata = rdata | 0x1;
1905 Xil_Out32(0xFD40289C, rdata);
1906
1907 do {
1908 if (count == 1100000)
1909 break;
1910 rdata = Xil_In32(0xFD402B1C);
1911 count++;
1912 } while ((rdata & 0x0000000E) != 0x0000000E);
1913
1914 for (i = 0; i < 23; i++) {
1915 match_pmos_code[i] = 0;
1916 match_nmos_code[i] = 0;
1917 }
1918 for (i = 0; i < 7; i++) {
1919 match_ical_code[i] = 0;
1920 match_rcal_code[i] = 0;
1921 }
1922
1923 do {
1924 Xil_Out32(0xFD410010, 0x00000000);
1925 Xil_Out32(0xFD410014, 0x00000000);
1926
1927 Xil_Out32(0xFD410010, 0x00000001);
1928 Xil_Out32(0xFD410014, 0x00000000);
1929
1930 maskstatus = mask_poll(0xFD40EF14, 0x2);
1931 if (maskstatus == 0) {
1932 xil_printf("#SERDES initialization timed out\n\r");
1933 return maskstatus;
1934 }
1935
1936 p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
1937 n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
1938 ;
1939 i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
1940 r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
1941 ;
1942
1943 if (p_code >= 0x26 && p_code <= 0x3C)
1944 match_pmos_code[p_code - 0x26] += 1;
1945
1946 if (n_code >= 0x26 && n_code <= 0x3C)
1947 match_nmos_code[n_code - 0x26] += 1;
1948
1949 if (i_code >= 0xC && i_code <= 0x12)
1950 match_ical_code[i_code - 0xc] += 1;
1951
1952 if (r_code >= 0x6 && r_code <= 0xC)
1953 match_rcal_code[r_code - 0x6] += 1;
1954
1955 } while (repeat_count++ < 10);
1956
1957 for (i = 0; i < 23; i++) {
1958 if (match_pmos_code[i] >= match_pmos_code[0]) {
1959 match_pmos_code[0] = match_pmos_code[i];
1960 p_code = 0x26 + i;
1961 }
1962 if (match_nmos_code[i] >= match_nmos_code[0]) {
1963 match_nmos_code[0] = match_nmos_code[i];
1964 n_code = 0x26 + i;
1965 }
1966 }
1967
1968 for (i = 0; i < 7; i++) {
1969 if (match_ical_code[i] >= match_ical_code[0]) {
1970 match_ical_code[0] = match_ical_code[i];
1971 i_code = 0xC + i;
1972 }
1973 if (match_rcal_code[i] >= match_rcal_code[0]) {
1974 match_rcal_code[0] = match_rcal_code[i];
1975 r_code = 0x6 + i;
1976 }
1977 }
1978
1979 L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
1980 L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
1981
1982 L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
1983 L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
1984 | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
1985
1986 L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
1987 L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
1988
1989 L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
1990 L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
1991
1992 L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
1993 L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
1994 | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
1995
1996 L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
1997 L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
1998
1999 Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
2000 Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
2001 Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
2002 Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
2003 Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
2004 Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
2005 return maskstatus;
2006}
2007
2008static int init_serdes(void)
2009{
2010 int status = 1;
2011
2012 status &= psu_resetin_init_data();
2013
2014 status &= serdes_fixcal_code();
2015 status &= serdes_enb_coarse_saturation();
2016
2017 status &= psu_serdes_init_data();
2018 status &= psu_resetout_init_data();
2019
2020 return status;
2021}
2022
2023static void init_peripheral(void)
2024{
2025 psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
2026}
2027
2028int psu_init(void)
2029{
2030 int status = 1;
2031
2032 status &= psu_mio_init_data();
2033 status &= psu_peripherals_pre_init_data();
2034 status &= psu_pll_init_data();
2035 status &= psu_clock_init_data();
2036 status &= psu_ddr_init_data();
2037 status &= psu_ddr_phybringup_data();
2038 status &= psu_peripherals_init_data();
2039 status &= init_serdes();
2040 init_peripheral();
2041
2042 status &= psu_afi_config();
2043 psu_ddr_qos_init_data();
2044
2045 if (status == 0)
2046 return 1;
2047 return 0;
2048}