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git01.mediatek.com / filogic / uboot / fd5c8845db8c3ce1d7cd29797cdf64ea188a8670 / . / arch / arm / dts / imx8mm-evk-u-boot.dtsi
blob: 9a5b0795133b379d7c82632bc9de9252bf804c2e [file] [log] [blame]
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]3 * Copyright 2019, 2021 NXP
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]4 */
5
Jagan Teki73d51182021-04-26 18:23:46 +0530[diff] [blame]6#include "imx8mm-u-boot.dtsi"
7
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]8/ {
9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]13 };
14};
15
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]16&aips4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]18};
19
Andrey Zhizhikincf51a552020-12-05 17:29:17 +0000[diff] [blame]20&reg_usdhc2_vmmc {
21 u-boot,off-on-delay-us = <20000>;
22};
23
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]24&pinctrl_reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]26};
27
28&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]30};
31
32&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]34};
35
36&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]38};
39
40&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]42};
43
44&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]46};
47
48&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]50};
51
52&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]54};
55
56&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]58};
59
60&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]62};
63
64&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]66};
67
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]68&usbmisc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]70};
71
72&usbphynop1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]74};
75
76&usbotg1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Fabio Estevam3cb058d2022-09-19 21:20:14 -0300[diff] [blame]78};
79
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]80&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]82};
83
84&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]86 sd-uhs-sdr104;
87 sd-uhs-ddr50;
Haibo Chen26154952021-03-22 18:55:38 +0800[diff] [blame]88 fsl,signal-voltage-switch-extra-delay-ms = <8>;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]89};
90
91&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]93 mmc-hs400-1_8v;
94 mmc-hs400-enhanced-strobe;
Peng Fanf9220172019-08-27 06:26:08 +0000[diff] [blame]95};
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]96
97&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-pre-ram;
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]99};
100
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200[diff] [blame]101&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-pre-ram;
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]103};
104
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200[diff] [blame]105&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-pre-ram;
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]107};
108
109&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-pre-ram;
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]111};
112
113&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-pre-ram;
Peng Fana9e04332019-10-16 10:24:42 +0000[diff] [blame]115};
Peng Fane5f2b222019-10-22 03:30:04 +0000[diff] [blame]116
Peng Fana279d682022-05-05 19:05:58 +0800[diff] [blame]117&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-pre-ram;
Peng Fana279d682022-05-05 19:05:58 +0800[diff] [blame]119};
120
Peng Fane5f2b222019-10-22 03:30:04 +0000[diff] [blame]121&fec1 {
122 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
123};
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]124
125&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Marek Vasut4512d502020-04-29 15:04:24 +0200[diff] [blame]127};