blob: 854bf2798aefd32df4cbc054ee285095bce26a30 [file] [log] [blame]
Marcel Ziswiler23b65be2022-07-21 15:27:35 +02001// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
Igor Opaniuk2213c892020-07-15 13:31:02 +03002/*
Marcel Ziswiler23b65be2022-07-21 15:27:35 +02003 * Copyright 2020-2022 Toradex
Igor Opaniuk2213c892020-07-15 13:31:02 +03004 */
5
Fabio Estevamee84bfe2023-09-12 12:11:00 -03006#include "imx7s-u-boot.dtsi"
7
Emanuele Ghidoliff939c22024-02-23 10:11:40 +01008/ {
9 aliases {
10 /* SDHCI instance order: eMMC, SD/MMC */
11 mmc0 = &usdhc3;
12 mmc1 = &usdhc1;
13 };
Emanuele Ghidoli26b5cba2024-02-23 10:11:41 +010014
15 sysinfo {
16 compatible = "toradex,sysinfo";
17 };
Marcel Ziswiler23b65be2022-07-21 15:27:35 +020018};
19
Igor Opaniuk2213c892020-07-15 13:31:02 +030020&lcdif {
21 status = "okay";
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_lcdif_dat
24 &pinctrl_lcdif_ctrl>;
25 display = <&display0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -070026 bootph-all;
Igor Opaniuk2213c892020-07-15 13:31:02 +030027
28 display0: display0 {
29 bits-per-pixel = <18>;
30 bus-width = <18>;
31 status = "okay";
32
33 display-timings {
34 native-mode = <&timing_vga>;
35 timing_vga: 640x480 {
36 clock-frequency = <25175000>;
37 hactive = <640>;
38 vactive = <480>;
39 hback-porch = <40>;
40 hfront-porch = <24>;
41 vback-porch = <32>;
42 vfront-porch = <11>;
43 hsync-len = <96>;
44 vsync-len = <2>;
45
46 de-active = <1>;
47 hsync-active = <0>;
48 vsync-active = <0>;
49 pixelclk-active = <0>;
50 };
51 };
52 };
53};
Parth Pancholi7d1c5062024-03-07 16:23:02 +010054
55&wdog1 {
56 bootph-pre-ram;
57};