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git01.mediatek.com / filogic / uboot / 9fe526db6e1dde0a8710a5c08aedb86dd02693b4 / . / arch / arm / dts / imx8mp-u-boot.dtsi
blob: 8b5ac3faf1c19eef5cd7f12d647e25e1fbce5c38 [file] [log] [blame]
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2021 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7/ {
8 binman: binman {
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]9 };
Tim Harvey2ae9f5a2023-08-24 12:01:43 -0700[diff] [blame]10
11#ifdef CONFIG_OPTEE
12 firmware {
13 optee {
14 compatible = "linaro,optee-tz";
15 method = "smc";
16 };
17 };
18#endif
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]19};
20
Tim Harvey0951b9a2023-08-24 12:03:56 -0700[diff] [blame]21#ifdef CONFIG_FSL_CAAM
22&crypto {
23 bootph-pre-ram;
24};
25#endif
26
Marcel Ziswilercdfde792022-11-07 22:22:39 +0100[diff] [blame]27&soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-all;
29 bootph-pre-ram;
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]30};
31
32&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
34 bootph-all;
Ye Lif93d54d2021-08-17 14:32:04 +0800[diff] [blame]35 /delete-property/ assigned-clocks;
36 /delete-property/ assigned-clock-parents;
37 /delete-property/ assigned-clock-rates;
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]38};
39
40&osc_32k {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
42 bootph-all;
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]43};
44
45&osc_24m {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
47 bootph-all;
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]48};
49
50&aips1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
52 bootph-all;
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]53};
54
55&aips2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]57};
58
59&aips3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Adam Ford0a357f92023-05-30 17:45:58 -0500[diff] [blame]61 spba-bus@30800000 {
62 bootph-pre-ram;
63 };
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]64};
65
66&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]68};
69
Tim Harvey0951b9a2023-08-24 12:03:56 -0700[diff] [blame]70#ifdef CONFIG_FSL_CAAM
71&sec_jr0 {
72 bootph-pre-ram;
73};
74
75&sec_jr1 {
76 bootph-pre-ram;
77};
78
79&sec_jr2 {
80 bootph-pre-ram;
81};
82#endif
83
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]84&binman {
Marek Vasutf44c7382024-04-26 01:00:37 +0200[diff] [blame]85 filename = "flash.bin";
86 section {
87 pad-byte = <0x00>;
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]88
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame^]89 binman_imx_spl: nxp-imx8mimage {
Marek Vasutf44c7382024-04-26 01:00:37 +0200[diff] [blame]90 filename = "u-boot-spl-mkimage.bin";
91 nxp,boot-from = "sd";
92 nxp,rom-version = <2>;
93 nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
94 args; /* Needed by mkimage etype superclass */
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]95
Marek Vasutf44c7382024-04-26 01:00:37 +0200[diff] [blame]96 section {
97 filename = "u-boot-spl-ddr.bin";
98 pad-byte = <0xff>;
99 align-size = <4>;
100 align = <4>;
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]101
Marek Vasutf44c7382024-04-26 01:00:37 +0200[diff] [blame]102 u-boot-spl {
103 align-end = <4>;
104 };
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]105
Marek Vasutf44c7382024-04-26 01:00:37 +0200[diff] [blame]106 ddr-1d-imem-fw {
107 filename = "lpddr4_pmu_train_1d_imem_202006.bin";
108 type = "blob-ext";
109 align-end = <4>;
110 };
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]111
Marek Vasutf44c7382024-04-26 01:00:37 +0200[diff] [blame]112 ddr-1d-dmem-fw {
113 filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
114 type = "blob-ext";
115 align-end = <4>;
116 };
Teresa Remmet1d05e8e2021-08-26 10:54:09 +0200[diff] [blame]117
Marek Vasutf44c7382024-04-26 01:00:37 +0200[diff] [blame]118 ddr-2d-imem-fw {
119 filename = "lpddr4_pmu_train_2d_imem_202006.bin";
120 type = "blob-ext";
121 align-end = <4>;
122 };
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]123
Marek Vasutf44c7382024-04-26 01:00:37 +0200[diff] [blame]124 ddr-2d-dmem-fw {
125 filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
126 type = "blob-ext";
127 align-end = <4>;
128 };
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]129 };
130 };
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]131
Marek Vasut9fe526d2024-05-21 12:48:24 +0200[diff] [blame^]132 binman_imx_fit: fit {
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]133 description = "Configuration to load ATF before U-Boot";
Marek Vasuta7416eb2023-05-28 23:00:30 +0200[diff] [blame]134#ifndef CONFIG_IMX_HAB
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]135 fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
Marek Vasuta7416eb2023-05-28 23:00:30 +0200[diff] [blame]136#endif
Tim Harvey65048742022-04-15 13:41:54 -0700[diff] [blame]137 fit,fdt-list = "of-list";
138 #address-cells = <1>;
Marek Vasutf44c7382024-04-26 01:00:37 +0200[diff] [blame]139 offset = <0x58000>;
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]140
141 images {
142 uboot {
143 description = "U-Boot (64-bit)";
144 type = "standalone";
145 arch = "arm64";
146 compression = "none";
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]147 load = <CONFIG_TEXT_BASE>;
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]148
149 uboot_blob: blob-ext {
150 filename = "u-boot-nodtb.bin";
151 };
152 };
153
Marek Vasut1de0eb12022-12-22 01:46:37 +0100[diff] [blame]154#ifndef CONFIG_ARMV8_PSCI
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]155 atf {
156 description = "ARM Trusted Firmware";
157 type = "firmware";
158 arch = "arm64";
159 compression = "none";
160 load = <0x970000>;
161 entry = <0x970000>;
162
Marcel Ziswilerd87d2f12022-04-08 10:06:56 +0200[diff] [blame]163 atf_blob: atf-blob {
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]164 filename = "bl31.bin";
Marcel Ziswilerd87d2f12022-04-08 10:06:56 +0200[diff] [blame]165 type = "atf-bl31";
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]166 };
167 };
Marek Vasut1de0eb12022-12-22 01:46:37 +0100[diff] [blame]168#endif
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]169
Tim Harvey65048742022-04-15 13:41:54 -0700[diff] [blame]170 @fdt-SEQ {
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]171 description = "NAME";
172 type = "flat_dt";
173 compression = "none";
174
Simon Glassceea7842023-08-23 19:18:01 -0600[diff] [blame]175 blob-ext {
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]176 filename = "u-boot.dtb";
177 };
178 };
179 };
180
181 configurations {
Tim Harvey65048742022-04-15 13:41:54 -0700[diff] [blame]182 default = "@config-DEFAULT-SEQ";
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]183
Simon Glassceea7842023-08-23 19:18:01 -0600[diff] [blame]184 @config-SEQ {
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]185 description = "NAME";
Tim Harvey65048742022-04-15 13:41:54 -0700[diff] [blame]186 fdt = "fdt-SEQ";
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]187 firmware = "uboot";
Marek Vasut1de0eb12022-12-22 01:46:37 +0100[diff] [blame]188#ifndef CONFIG_ARMV8_PSCI
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]189 loadables = "atf";
Marek Vasut1de0eb12022-12-22 01:46:37 +0100[diff] [blame]190#endif
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]191 };
192 };
193 };
194 };
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]195};