blob: 41deeda64411e504684b1e2358fb2d1c4af4b8a6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocherf1084d62011-11-01 20:00:31 +00002/*
3 * Copyright (C) 2011
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
Heiko Schocherf1084d62011-11-01 20:00:31 +00005 */
6#ifndef _DV_SYSCFG_DEFS_H_
7#define _DV_SYSCFG_DEFS_H_
8
9#ifndef CONFIG_SOC_DA8XX
10/* System Control Module register structure for DM365 */
11struct dv_sys_module_regs {
12 unsigned int pinmux[5]; /* 0x00 */
13 unsigned int bootcfg; /* 0x14 */
14 unsigned int arm_intmux; /* 0x18 */
15 unsigned int edma_evtmux; /* 0x1C */
16 unsigned int ddr_slew; /* 0x20 */
17 unsigned int clkout; /* 0x24 */
18 unsigned int device_id; /* 0x28 */
19 unsigned int vdac_config; /* 0x2C */
20 unsigned int timer64_ctl; /* 0x30 */
21 unsigned int usbbphy_ctl; /* 0x34 */
22 unsigned int misc; /* 0x38 */
23 unsigned int mstpri[2]; /* 0x3C */
24 unsigned int vpss_clkctl; /* 0x44 */
25 unsigned int peri_clkctl; /* 0x48 */
26 unsigned int deepsleep; /* 0x4C */
27 unsigned int dft_enable; /* 0x50 */
28 unsigned int debounce[8]; /* 0x54 */
29 unsigned int vtpiocr; /* 0x74 */
30 unsigned int pupdctl0; /* 0x78 */
31 unsigned int pupdctl1; /* 0x7C */
32 unsigned int hdimcopbt; /* 0x80 */
33 unsigned int pll0_config; /* 0x84 */
34 unsigned int pll1_config; /* 0x88 */
35};
36
37#define VPTIO_RDY (1 << 15)
38#define VPTIO_IOPWRDN (1 << 14)
39#define VPTIO_CLRZ (1 << 13)
40#define VPTIO_LOCK (1 << 7)
41#define VPTIO_PWRDN (1 << 6)
42
43#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
44
45#define dv_sys_module_regs \
46 ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
47
48#endif /* !CONFIG_SOC_DA8XX */
49#endif /* _DV_SYSCFG_DEFS_H_ */