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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Shengzhou Liu07886942013-11-22 17:39:11 +08002/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
Shengzhou Liu07886942013-11-22 17:39:11 +08004 */
5
6#ifndef __DDR_H__
7#define __DDR_H__
8struct board_specific_parameters {
9 u32 n_ranks;
10 u32 datarate_mhz_high;
11 u32 rank_gb;
12 u32 clk_adjust;
13 u32 wrlvl_start;
14 u32 wrlvl_ctl_2;
15 u32 wrlvl_ctl_3;
Shengzhou Liu07886942013-11-22 17:39:11 +080016};
17
18/*
19 * These tables contain all valid speeds we want to override with board
20 * specific parameters. datarate_mhz_high values need to be in ascending order
21 * for each n_ranks group.
22 */
23
24static const struct board_specific_parameters udimm0[] = {
25 /*
26 * memory controller 0
Shengzhou Liueca52382014-05-20 12:08:20 +080027 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
Shengzhou Liu07886942013-11-22 17:39:11 +080029 */
Shengzhou Liuf1510e62016-05-04 10:20:22 +080030 {2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09},
31 {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a},
32 {2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c},
33 {2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d},
34 {2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d},
35 {1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a},
36 {1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09},
37 {1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b},
38 {1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a},
39 {1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c},
40 {1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b},
Shengzhou Liu07886942013-11-22 17:39:11 +080041 {}
42};
43
44static const struct board_specific_parameters rdimm0[] = {
45 /*
46 * memory controller 0
Shengzhou Liu660225b2014-01-13 13:01:06 +080047 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
48 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
Shengzhou Liu07886942013-11-22 17:39:11 +080049 */
Shengzhou Liu660225b2014-01-13 13:01:06 +080050 /* TODO: need tuning these parameters if RDIMM is used */
Shengzhou Liuf1510e62016-05-04 10:20:22 +080051 {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
52 {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
53 {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
54 {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
55 {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
56 {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
57 {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
58 {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
59 {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
Shengzhou Liu07886942013-11-22 17:39:11 +080060 {}
61};
62
Shengzhou Liu07886942013-11-22 17:39:11 +080063static const struct board_specific_parameters *udimms[] = {
64 udimm0,
65};
66
Shengzhou Liu07886942013-11-22 17:39:11 +080067static const struct board_specific_parameters *rdimms[] = {
68 rdimm0,
69};
Shengzhou Liu07886942013-11-22 17:39:11 +080070#endif