Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2016 Freescale Semiconductor |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __LS1046ARDB_H__ |
| 7 | #define __LS1046ARDB_H__ |
| 8 | |
| 9 | #include "ls1046a_common.h" |
| 10 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 11 | #define CONFIG_SYS_CLK_FREQ 100000000 |
| 12 | #define CONFIG_DDR_CLK_FREQ 100000000 |
| 13 | |
| 14 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 15 | |
| 16 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 17 | /* Physical Memory Map */ |
| 18 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 19 | |
| 20 | #define CONFIG_DDR_SPD |
| 21 | #define SPD_EEPROM_ADDRESS 0x51 |
| 22 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 23 | |
| 24 | #define CONFIG_DDR_ECC |
| 25 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 26 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 27 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 28 | #ifdef CONFIG_SD_BOOT |
York Sun | 3e512d8 | 2018-06-26 14:48:29 -0700 | [diff] [blame] | 29 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 30 | #ifdef CONFIG_EMMC_BOOT |
| 31 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 32 | board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |
| 33 | #else |
| 34 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg |
| 35 | #endif |
York Sun | 3e512d8 | 2018-06-26 14:48:29 -0700 | [diff] [blame] | 36 | #elif defined(CONFIG_QSPI_BOOT) |
| 37 | #define CONFIG_SYS_FSL_PBL_RCW \ |
| 38 | board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg |
| 39 | #define CONFIG_SYS_FSL_PBL_PBI \ |
| 40 | board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg |
| 41 | #define CONFIG_SYS_UBOOT_BASE 0x40100000 |
| 42 | #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 43 | #endif |
| 44 | |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 45 | #ifndef SPL_NO_IFC |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 46 | /* IFC */ |
| 47 | #define CONFIG_FSL_IFC |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 48 | /* |
| 49 | * NAND Flash Definitions |
| 50 | */ |
| 51 | #define CONFIG_NAND_FSL_IFC |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 52 | #endif |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 53 | |
| 54 | #define CONFIG_SYS_NAND_BASE 0x7e800000 |
| 55 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 56 | |
| 57 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) |
| 58 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 59 | | CSPR_PORT_SIZE_8 \ |
| 60 | | CSPR_MSEL_NAND \ |
| 61 | | CSPR_V) |
| 62 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) |
| 63 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 64 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 65 | | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ |
| 66 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ |
| 67 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ |
| 68 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ |
| 69 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ |
| 70 | |
| 71 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 72 | |
| 73 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ |
| 74 | FTIM0_NAND_TWP(0x18) | \ |
| 75 | FTIM0_NAND_TWCHT(0x7) | \ |
| 76 | FTIM0_NAND_TWH(0xa)) |
| 77 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
| 78 | FTIM1_NAND_TWBE(0x39) | \ |
| 79 | FTIM1_NAND_TRR(0xe) | \ |
| 80 | FTIM1_NAND_TRP(0x18)) |
| 81 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ |
| 82 | FTIM2_NAND_TREH(0xa) | \ |
| 83 | FTIM2_NAND_TWHRE(0x1e)) |
| 84 | #define CONFIG_SYS_NAND_FTIM3 0x0 |
| 85 | |
| 86 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 87 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 88 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 89 | |
| 90 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 91 | |
| 92 | /* |
| 93 | * CPLD |
| 94 | */ |
| 95 | #define CONFIG_SYS_CPLD_BASE 0x7fb00000 |
| 96 | #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE |
| 97 | |
| 98 | #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) |
| 99 | #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ |
| 100 | CSPR_PORT_SIZE_8 | \ |
| 101 | CSPR_MSEL_GPCM | \ |
| 102 | CSPR_V) |
| 103 | #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) |
| 104 | #define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) |
| 105 | |
| 106 | /* CPLD Timing parameters for IFC GPCM */ |
| 107 | #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
| 108 | FTIM0_GPCM_TEADC(0x0e) | \ |
| 109 | FTIM0_GPCM_TEAHC(0x0e)) |
| 110 | #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
| 111 | FTIM1_GPCM_TRAD(0x3f)) |
| 112 | #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
| 113 | FTIM2_GPCM_TCH(0xf) | \ |
| 114 | FTIM2_GPCM_TWP(0x3E)) |
| 115 | #define CONFIG_SYS_CPLD_FTIM3 0x0 |
| 116 | |
| 117 | /* IFC Timing Params */ |
| 118 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 119 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 120 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
| 121 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
| 122 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 123 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 124 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 125 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 126 | |
| 127 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT |
| 128 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR |
| 129 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK |
| 130 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR |
| 131 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 |
| 132 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 |
| 133 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 |
| 134 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 |
| 135 | |
| 136 | /* EEPROM */ |
| 137 | #define CONFIG_ID_EEPROM |
| 138 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 139 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 140 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 |
| 141 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 142 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 143 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
| 144 | #define I2C_RETIMER_ADDR 0x18 |
| 145 | |
Hou Zhiqiang | 67b6d0a | 2016-12-09 16:09:01 +0800 | [diff] [blame] | 146 | /* PMIC */ |
| 147 | #define CONFIG_POWER |
| 148 | #ifdef CONFIG_POWER |
| 149 | #define CONFIG_POWER_I2C |
| 150 | #endif |
| 151 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 152 | /* |
| 153 | * Environment |
| 154 | */ |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 155 | #ifndef SPL_NO_ENV |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 156 | #define CONFIG_ENV_OVERWRITE |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 157 | #endif |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 158 | |
Rajesh Bhagat | cb6153b | 2018-11-05 18:02:36 +0000 | [diff] [blame] | 159 | #ifdef CONFIG_TFABOOT |
| 160 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 161 | |
| 162 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 163 | #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ |
| 164 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ |
| 165 | #else |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 166 | #if defined(CONFIG_SD_BOOT) |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 167 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
Alison Wang | 42f3780 | 2017-05-16 10:45:59 +0800 | [diff] [blame] | 168 | #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 169 | #define CONFIG_ENV_SIZE 0x2000 |
| 170 | #else |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 171 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
Alison Wang | 42f3780 | 2017-05-16 10:45:59 +0800 | [diff] [blame] | 172 | #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 173 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ |
| 174 | #endif |
Rajesh Bhagat | cb6153b | 2018-11-05 18:02:36 +0000 | [diff] [blame] | 175 | #endif |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 176 | |
York Sun | 624b657 | 2017-04-25 08:39:51 -0700 | [diff] [blame] | 177 | #define AQR105_IRQ_MASK 0x80000000 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 178 | /* FMan */ |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 179 | #ifndef SPL_NO_FMAN |
York Sun | 624b657 | 2017-04-25 08:39:51 -0700 | [diff] [blame] | 180 | |
| 181 | #ifdef CONFIG_NET |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 182 | #define CONFIG_PHY_REALTEK |
York Sun | 624b657 | 2017-04-25 08:39:51 -0700 | [diff] [blame] | 183 | #endif |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 184 | |
York Sun | 624b657 | 2017-04-25 08:39:51 -0700 | [diff] [blame] | 185 | #ifdef CONFIG_SYS_DPAA_FMAN |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 186 | #define RGMII_PHY1_ADDR 0x1 |
| 187 | #define RGMII_PHY2_ADDR 0x2 |
| 188 | |
| 189 | #define SGMII_PHY1_ADDR 0x3 |
| 190 | #define SGMII_PHY2_ADDR 0x4 |
| 191 | |
| 192 | #define FM1_10GEC1_PHY_ADDR 0x0 |
| 193 | |
Prabhakar Kushwaha | a512261 | 2017-11-23 16:51:48 +0530 | [diff] [blame] | 194 | #define FDT_SEQ_MACADDR_FROM_ENV |
| 195 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 196 | #define CONFIG_ETHPRIME "FM1@DTSEC3" |
| 197 | #endif |
York Sun | 624b657 | 2017-04-25 08:39:51 -0700 | [diff] [blame] | 198 | |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 199 | #endif |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 200 | |
| 201 | /* QSPI device */ |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 202 | #ifndef SPL_NO_QSPI |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 203 | #ifdef CONFIG_FSL_QSPI |
| 204 | #define CONFIG_SPI_FLASH_SPANSION |
| 205 | #define FSL_QSPI_FLASH_SIZE (1 << 26) |
| 206 | #define FSL_QSPI_FLASH_NUM 2 |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 207 | #endif |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 208 | #endif |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 209 | |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 210 | #ifndef SPL_NO_MISC |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 211 | #undef CONFIG_BOOTCOMMAND |
Rajesh Bhagat | cb6153b | 2018-11-05 18:02:36 +0000 | [diff] [blame] | 212 | #ifdef CONFIG_TFABOOT |
| 213 | #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ |
| 214 | "env exists secureboot && esbc_halt;;" |
| 215 | #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ |
| 216 | "env exists secureboot && esbc_halt;" |
| 217 | #else |
Shengzhou Liu | 47e7e03 | 2017-11-09 17:57:56 +0800 | [diff] [blame] | 218 | #if defined(CONFIG_QSPI_BOOT) |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 219 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ |
| 220 | "env exists secureboot && esbc_halt;;" |
Shengzhou Liu | 47e7e03 | 2017-11-09 17:57:56 +0800 | [diff] [blame] | 221 | #elif defined(CONFIG_SD_BOOT) |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 222 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ |
| 223 | "env exists secureboot && esbc_halt;" |
Shengzhou Liu | 47e7e03 | 2017-11-09 17:57:56 +0800 | [diff] [blame] | 224 | #endif |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 225 | #endif |
Rajesh Bhagat | cb6153b | 2018-11-05 18:02:36 +0000 | [diff] [blame] | 226 | #endif |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 227 | |
Vinitha Pillai-B57223 | a47072e | 2017-03-23 13:48:18 +0530 | [diff] [blame] | 228 | #include <asm/fsl_secure_boot.h> |
| 229 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 230 | #endif /* __LS1046ARDB_H__ */ |