| Bin Meng | 09360af | 2019-07-18 00:34:06 -0700 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ |
| 2 | .. sectionauthor:: Simon Glass <sjg@chromium.org> |
| 3 | |
| 4 | Minnowboard MAX |
| 5 | =============== |
| 6 | |
| 7 | This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. |
| 8 | Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at |
| 9 | the time of writing). Put it in the corresponding board directory and rename |
| 10 | it to fsp.bin. |
| 11 | |
| 12 | Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same |
| 13 | board directory as vga.bin. |
| 14 | |
| 15 | You still need two more binary blobs. For Minnowboard MAX, we can reuse the |
| 16 | same ME firmware above, but for flash descriptor, we need get that somewhere |
| 17 | else, as the one above does not seem to work, probably because it is not |
| 18 | designed for the Minnowboard MAX. Now download the original firmware image |
| 19 | for this board from: |
| 20 | |
| 21 | * http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip |
| 22 | |
| 23 | Unzip it:: |
| 24 | |
| 25 | $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip |
| 26 | |
| 27 | Use ifdtool in the U-Boot tools directory to extract the images from that |
| 28 | file, for example:: |
| 29 | |
| 30 | $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin |
| 31 | |
| 32 | This will provide the descriptor file - copy this into the correct place:: |
| 33 | |
| 34 | $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin |
| 35 | |
| 36 | Now you can build U-Boot and obtain u-boot.rom:: |
| 37 | |
| 38 | $ make minnowmax_defconfig |
| 39 | $ make all |
| 40 | |
| 41 | Checksums are as follows (but note that newer versions will invalidate this):: |
| 42 | |
| 43 | $ md5sum -b board/intel/minnowmax/*.bin |
| 44 | ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin |
| 45 | 69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin |
| 46 | 894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin |
| 47 | a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin |
| 48 | |
| 49 | The ROM image is broken up into these parts: |
| 50 | |
| 51 | ====== ================== ============================ |
| 52 | Offset Description Controlling config |
| 53 | ====== ================== ============================ |
| 54 | 000000 descriptor.bin Hard-coded to 0 in ifdtool |
| 55 | 001000 me.bin Set by the descriptor |
| 56 | 500000 <spare> |
| 57 | 6ef000 Environment CONFIG_ENV_OFFSET |
| 58 | 6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE |
| Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 59 | 700000 u-boot-dtb.bin CONFIG_TEXT_BASE |
| Bin Meng | 09360af | 2019-07-18 00:34:06 -0700 | [diff] [blame] | 60 | 7b0000 vga.bin CONFIG_VGA_BIOS_ADDR |
| 61 | 7c0000 fsp.bin CONFIG_FSP_ADDR |
| 62 | 7f8000 <spare> (depends on size of fsp.bin) |
| 63 | 7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16 |
| 64 | ====== ================== ============================ |
| 65 | |
| 66 | Overall ROM image size is controlled by CONFIG_ROM_SIZE. |
| 67 | |
| 68 | Note that the debug version of the FSP is bigger in size. If this version |
| 69 | is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of |
| 70 | the default value 0xfffc0000. |