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Parthiban Nallathambi5e9147d2019-04-18 00:04:09 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Board configuration file for Variscite DART-6UL Evaluation Kit
4 * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
5 */
6#ifndef __DART_6UL_H
7#define __DART_6UL_H
8
9#include <linux/sizes.h>
Simon Glassfb64e362020-05-10 11:40:09 -060010#include <linux/stringify.h>
Parthiban Nallathambi5e9147d2019-04-18 00:04:09 +020011#include "mx6_common.h"
12
13/* SPL options */
14#include "imx6_spl.h"
15
16/* NAND pin conflicts with usdhc2 */
17#ifdef CONFIG_CMD_NAND
18#define CONFIG_SYS_FSL_USDHC_NUM 1
19#else
20#define CONFIG_SYS_FSL_USDHC_NUM 2
21#endif
22
23#ifdef CONFIG_CMD_NET
24#define CONFIG_FEC_ENET_DEV 0
25
26#if (CONFIG_FEC_ENET_DEV == 0)
27#define IMX_FEC_BASE ENET_BASE_ADDR
28#define CONFIG_FEC_MXC_PHYADDR 0x1
29#define CONFIG_FEC_XCV_TYPE RMII
30#define CONFIG_ETHPRIME "eth0"
31#elif (CONFIG_FEC_ENET_DEV == 1)
32#define IMX_FEC_BASE ENET2_BASE_ADDR
33#define CONFIG_FEC_MXC_PHYADDR 0x3
34#define CONFIG_FEC_XCV_TYPE RMII
35#define CONFIG_ETHPRIME "eth1"
36#endif
37#endif
38
39/* Size of malloc() pool */
40#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
41
42/* Environment settings */
Parthiban Nallathambi5e9147d2019-04-18 00:04:09 +020043
44/* Environment in SD */
45#define CONFIG_SYS_MMC_ENV_DEV 0
46#define CONFIG_SYS_MMC_ENV_PART 0
47#define MMC_ROOTFS_DEV 0
48#define MMC_ROOTFS_PART 2
49
50/* Console configs */
51#define CONFIG_MXC_UART_BASE UART1_BASE
52
53/* MMC Configs */
Parthiban Nallathambi5e9147d2019-04-18 00:04:09 +020054
55#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
56#define CONFIG_SUPPORT_EMMC_BOOT
57
58/* I2C configs */
59#ifdef CONFIG_CMD_I2C
60#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
61#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
62#define CONFIG_SYS_I2C_SPEED 100000
63#endif
64
65/* Miscellaneous configurable options */
Parthiban Nallathambi5e9147d2019-04-18 00:04:09 +020066
67#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
68#define CONFIG_SYS_HZ 1000
69
70/* Physical Memory Map */
71#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
72#define PHYS_SDRAM_SIZE SZ_512M
73
74#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
75#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
76#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
77
78#define CONFIG_SYS_INIT_SP_OFFSET \
79 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
80#define CONFIG_SYS_INIT_SP_ADDR \
81 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
82
83/* USB Configs */
84#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
85#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
86#define CONFIG_MXC_USB_FLAGS 0
87#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
88
89#define CONFIG_IMX_THERMAL
90
91#define ENV_MMC \
92 "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
93 "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
94 "fitpart=1\0" \
95 "bootdelay=3\0" \
96 "silent=1\0" \
97 "optargs=rw rootwait\0" \
98 "mmcautodetect=yes\0" \
99 "mmcrootfstype=ext4\0" \
100 "mmcfit_name=fitImage\0" \
101 "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
102 "${mmcfit_name}\0" \
103 "mmcargs=setenv bootargs " \
104 "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \
105 "console=${console} rootfstype=${mmcrootfstype}\0" \
106 "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \
107
108/* Default environment */
109#define CONFIG_EXTRA_ENV_SETTINGS \
110 "fdt_high=0xffffffff\0" \
111 "console=ttymxc0,115200n8\0" \
112 "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
113 "fit_addr=0x82000000\0" \
114 ENV_MMC
115
116#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit"
117
118#define BOOT_TARGET_DEVICES(func) \
119 func(MMC, mmc, 0) \
120 func(MMC, mmc, 1) \
121 func(DHCP, dhcp, na)
122
123#include <config_distro_bootcmd.h>
124#endif /* __DART_6UL_H */