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York Sune12abcb2015-03-20 19:28:24 -07001/*
2 * Copyright 2015 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS2_RDB_H
8#define __LS2_RDB_H
9
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053010#include "ls2080a_common.h"
York Sune12abcb2015-03-20 19:28:24 -070011
12#undef CONFIG_CONS_INDEX
13#define CONFIG_CONS_INDEX 2
14
Rai Harninder6aa1f3b2016-03-23 17:04:38 +053015#define I2C_MUX_CH_VOL_MONITOR 0xa
16#define I2C_VOL_MONITOR_ADDR 0x38
17#define CONFIG_VOL_MONITOR_IR36021_READ
18#define CONFIG_VOL_MONITOR_IR36021_SET
19
20#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
21#ifndef CONFIG_SPL_BUILD
22#define CONFIG_VID
23#endif
24/* step the IR regulator in 5mV increments */
25#define IR_VDD_STEP_DOWN 5
26#define IR_VDD_STEP_UP 5
27/* The lowest and highest voltage allowed for LS2080ARDB */
28#define VDD_MV_MIN 819
29#define VDD_MV_MAX 1212
30
York Sune12abcb2015-03-20 19:28:24 -070031#ifndef __ASSEMBLY__
32unsigned long get_board_sys_clk(void);
33#endif
34
Gong Qianyu52de2e52015-10-26 19:47:42 +080035#define CONFIG_SYS_FSL_CLK
York Sune12abcb2015-03-20 19:28:24 -070036#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
37#define CONFIG_DDR_CLK_FREQ 133333333
38#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
39
40#define CONFIG_DDR_SPD
41#define CONFIG_DDR_ECC
42#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
43#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
44#define SPD_EEPROM_ADDRESS1 0x51
45#define SPD_EEPROM_ADDRESS2 0x52
York Sunac192a92015-05-28 14:54:09 +053046#define SPD_EEPROM_ADDRESS3 0x53
47#define SPD_EEPROM_ADDRESS4 0x54
York Sune12abcb2015-03-20 19:28:24 -070048#define SPD_EEPROM_ADDRESS5 0x55
49#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
50#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
51#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
52#define CONFIG_DIMM_SLOTS_PER_CTLR 2
53#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053054#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sune12abcb2015-03-20 19:28:24 -070055#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053056#endif
York Sune12abcb2015-03-20 19:28:24 -070057#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
58
Tang Yuantian57894be2015-12-09 15:32:18 +080059/* SATA */
60#define CONFIG_LIBATA
61#define CONFIG_SCSI_AHCI
62#define CONFIG_SCSI_AHCI_PLAT
Simon Glass8706b812016-05-01 11:36:02 -060063#define CONFIG_SCSI
Tang Yuantian57894be2015-12-09 15:32:18 +080064#define CONFIG_DOS_PARTITION
65#define CONFIG_BOARD_LATE_INIT
66
67#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
68#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
69
70#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
71#define CONFIG_SYS_SCSI_MAX_LUN 1
72#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
73 CONFIG_SYS_SCSI_MAX_LUN)
74
York Sune12abcb2015-03-20 19:28:24 -070075/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
76
77#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
78#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
79#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
80
81#define CONFIG_SYS_NOR0_CSPR \
82 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
83 CSPR_PORT_SIZE_16 | \
84 CSPR_MSEL_NOR | \
85 CSPR_V)
86#define CONFIG_SYS_NOR0_CSPR_EARLY \
87 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
88 CSPR_PORT_SIZE_16 | \
89 CSPR_MSEL_NOR | \
90 CSPR_V)
91#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
92#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
93 FTIM0_NOR_TEADC(0x5) | \
94 FTIM0_NOR_TEAHC(0x5))
95#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
96 FTIM1_NOR_TRAD_NOR(0x1a) |\
97 FTIM1_NOR_TSEQRAD_NOR(0x13))
98#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
99 FTIM2_NOR_TCH(0x4) | \
100 FTIM2_NOR_TWPH(0x0E) | \
101 FTIM2_NOR_TWP(0x1c))
102#define CONFIG_SYS_NOR_FTIM3 0x04000000
103#define CONFIG_SYS_IFC_CCR 0x01000000
104
105#ifndef CONFIG_SYS_NO_FLASH
106#define CONFIG_FLASH_CFI_DRIVER
107#define CONFIG_SYS_FLASH_CFI
108#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
109#define CONFIG_SYS_FLASH_QUIET_TEST
110#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
111
112#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
113#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
114#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
115#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
116
117#define CONFIG_SYS_FLASH_EMPTY_INFO
118#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
119 CONFIG_SYS_FLASH_BASE + 0x40000000}
120#endif
121
122#define CONFIG_NAND_FSL_IFC
123#define CONFIG_SYS_NAND_MAX_ECCPOS 256
124#define CONFIG_SYS_NAND_MAX_OOBFREE 2
125
York Sune12abcb2015-03-20 19:28:24 -0700126#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
127#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
128 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
129 | CSPR_MSEL_NAND /* MSEL = NAND */ \
130 | CSPR_V)
131#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
132
133#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
134 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
135 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
136 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
137 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
138 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
139 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
140
141#define CONFIG_SYS_NAND_ONFI_DETECTION
142
143/* ONFI NAND Flash mode0 Timing Params */
144#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
145 FTIM0_NAND_TWP(0x30) | \
146 FTIM0_NAND_TWCHT(0x0e) | \
147 FTIM0_NAND_TWH(0x14))
148#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
149 FTIM1_NAND_TWBE(0xab) | \
150 FTIM1_NAND_TRR(0x1c) | \
151 FTIM1_NAND_TRP(0x30))
152#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
153 FTIM2_NAND_TREH(0x14) | \
154 FTIM2_NAND_TWHRE(0x3c))
155#define CONFIG_SYS_NAND_FTIM3 0x0
156
157#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
158#define CONFIG_SYS_MAX_NAND_DEVICE 1
159#define CONFIG_MTD_NAND_VERIFY_WRITE
160#define CONFIG_CMD_NAND
161
162#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
163
164#define CONFIG_FSL_QIXIS /* use common QIXIS code */
165#define QIXIS_LBMAP_SWITCH 0x06
166#define QIXIS_LBMAP_MASK 0x0f
167#define QIXIS_LBMAP_SHIFT 0
168#define QIXIS_LBMAP_DFLTBANK 0x00
169#define QIXIS_LBMAP_ALTBANK 0x04
Scott Wood212b8d82015-03-24 13:25:03 -0700170#define QIXIS_LBMAP_NAND 0x09
York Sune12abcb2015-03-20 19:28:24 -0700171#define QIXIS_RST_CTL_RESET 0x31
172#define QIXIS_RST_CTL_RESET_EN 0x30
173#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
174#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
175#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Scott Wood212b8d82015-03-24 13:25:03 -0700176#define QIXIS_RCW_SRC_NAND 0x119
York Sune12abcb2015-03-20 19:28:24 -0700177#define QIXIS_RST_FORCE_MEM 0x01
178
179#define CONFIG_SYS_CSPR3_EXT (0x0)
180#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
181 | CSPR_PORT_SIZE_8 \
182 | CSPR_MSEL_GPCM \
183 | CSPR_V)
184#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
185 | CSPR_PORT_SIZE_8 \
186 | CSPR_MSEL_GPCM \
187 | CSPR_V)
188
189#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
190#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
191/* QIXIS Timing parameters for IFC CS3 */
192#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
193 FTIM0_GPCM_TEADC(0x0e) | \
194 FTIM0_GPCM_TEAHC(0x0e))
195#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
196 FTIM1_GPCM_TRAD(0x3f))
197#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
198 FTIM2_GPCM_TCH(0xf) | \
199 FTIM2_GPCM_TWP(0x3E))
200#define CONFIG_SYS_CS3_FTIM3 0x0
201
Scott Wood212b8d82015-03-24 13:25:03 -0700202#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
203#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
204#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
205#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
206#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
207#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
208#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
209#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
210#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
211#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
212#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
213#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
214#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
215#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
216#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
217#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
218#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
219#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
220
221#define CONFIG_ENV_IS_IN_NAND
222#define CONFIG_ENV_OFFSET (2048 * 1024)
223#define CONFIG_ENV_SECT_SIZE 0x20000
224#define CONFIG_ENV_SIZE 0x2000
225#define CONFIG_SPL_PAD_TO 0x80000
226#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
227#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
228#else
York Sune12abcb2015-03-20 19:28:24 -0700229#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
230#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
231#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
232#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
233#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
234#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
235#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
236#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
237#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
238#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
239#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
240#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
241#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
242#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
243#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
244#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
245#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
246
Scott Wood212b8d82015-03-24 13:25:03 -0700247#define CONFIG_ENV_IS_IN_FLASH
248#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
249#define CONFIG_ENV_SECT_SIZE 0x20000
250#define CONFIG_ENV_SIZE 0x2000
251#endif
252
York Sune12abcb2015-03-20 19:28:24 -0700253/* Debug Server firmware */
254#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
255#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
256
York Sune12abcb2015-03-20 19:28:24 -0700257#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
258
259/*
260 * I2C
261 */
Prabhakar Kushwahad561e2d2015-05-28 14:54:01 +0530262#define I2C_MUX_PCA_ADDR 0x75
263#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
York Sune12abcb2015-03-20 19:28:24 -0700264
265/* I2C bus multiplexer */
266#define I2C_MUX_CH_DEFAULT 0x8
267
Haikun Wang7e3180d2015-07-03 16:51:35 +0800268/* SPI */
269#ifdef CONFIG_FSL_DSPI
Haikun Wang7e3180d2015-07-03 16:51:35 +0800270#define CONFIG_SPI_FLASH
Haikun Wang7e3180d2015-07-03 16:51:35 +0800271#define CONFIG_SPI_FLASH_BAR
272#endif
273
York Sune12abcb2015-03-20 19:28:24 -0700274/*
275 * RTC configuration
276 */
277#define RTC
278#define CONFIG_RTC_DS3231 1
279#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Priyanka Jain2a2e8202015-05-28 14:53:56 +0530280#define CONFIG_CMD_DATE
York Sune12abcb2015-03-20 19:28:24 -0700281
282/* EEPROM */
283#define CONFIG_ID_EEPROM
284#define CONFIG_CMD_EEPROM
285#define CONFIG_SYS_I2C_EEPROM_NXID
286#define CONFIG_SYS_EEPROM_BUS_NUM 0
287#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
288#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
289#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
290#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
291
York Sune12abcb2015-03-20 19:28:24 -0700292#define CONFIG_FSL_MEMAC
York Sune12abcb2015-03-20 19:28:24 -0700293#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
294
295#ifdef CONFIG_PCI
York Sune12abcb2015-03-20 19:28:24 -0700296#define CONFIG_PCI_SCAN_SHOW
297#define CONFIG_CMD_PCI
York Sune12abcb2015-03-20 19:28:24 -0700298#endif
299
Yangbo Lud0e295d2015-03-20 19:28:31 -0700300/* MMC */
301#define CONFIG_MMC
302#ifdef CONFIG_MMC
Yangbo Lud0e295d2015-03-20 19:28:31 -0700303#define CONFIG_FSL_ESDHC
304#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
305#define CONFIG_GENERIC_MMC
Yangbo Lud0e295d2015-03-20 19:28:31 -0700306#define CONFIG_DOS_PARTITION
307#endif
York Sune12abcb2015-03-20 19:28:24 -0700308
Yangbo Lucf005552015-05-28 14:53:55 +0530309#define CONFIG_MISC_INIT_R
310
Nikhil Badola817c1f02015-06-26 17:02:18 +0530311/*
312 * USB
313 */
314#define CONFIG_HAS_FSL_XHCI_USB
Nikhil Badola817c1f02015-06-26 17:02:18 +0530315#define CONFIG_USB_XHCI_FSL
Nikhil Badola817c1f02015-06-26 17:02:18 +0530316#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
317#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
Nikhil Badola817c1f02015-06-26 17:02:18 +0530318
York Sune12abcb2015-03-20 19:28:24 -0700319/* Initial environment variables */
320#undef CONFIG_EXTRA_ENV_SETTINGS
321#define CONFIG_EXTRA_ENV_SETTINGS \
322 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
323 "loadaddr=0x80100000\0" \
324 "kernel_addr=0x100000\0" \
325 "ramdisk_addr=0x800000\0" \
326 "ramdisk_size=0x2000000\0" \
327 "fdt_high=0xa0000000\0" \
328 "initrd_high=0xffffffffffffffff\0" \
329 "kernel_start=0x581100000\0" \
330 "kernel_load=0xa0000000\0" \
Prabhakar Kushwahaae193f92016-02-03 17:03:51 +0530331 "kernel_size=0x2800000\0" \
332 "mcinitcmd=fsl_mc start mc 0x580300000" \
333 " 0x580800000 \0"
York Sune12abcb2015-03-20 19:28:24 -0700334
Prabhakar Kushwahaf4392592015-08-02 09:11:44 +0530335#undef CONFIG_BOOTARGS
336#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
York Sun15b2c802016-02-29 15:58:20 -0800337 "earlycon=uart8250,mmio,0x21c0600 " \
Prabhakar Kushwahaf4392592015-08-02 09:11:44 +0530338 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
Ashish Kumara7161db2016-01-14 18:12:29 +0530339 " hugepagesz=2m hugepages=256"
Prabhakar Kushwahaf4392592015-08-02 09:11:44 +0530340
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530341/* MAC/PHY configuration */
342#ifdef CONFIG_FSL_MC_ENET
343#define CONFIG_PHYLIB_10G
Shaohui Xie3d3a7b92015-09-24 18:20:32 +0800344#define CONFIG_PHY_AQUANTIA
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530345#define CONFIG_PHY_CORTINA
346#define CONFIG_PHYLIB
347#define CONFIG_SYS_CORTINA_FW_IN_NOR
348#define CONFIG_CORTINA_FW_ADDR 0x581000000
349#define CONFIG_CORTINA_FW_LENGTH 0x40000
350
351#define CORTINA_PHY_ADDR1 0x10
352#define CORTINA_PHY_ADDR2 0x11
353#define CORTINA_PHY_ADDR3 0x12
354#define CORTINA_PHY_ADDR4 0x13
355#define AQ_PHY_ADDR1 0x00
356#define AQ_PHY_ADDR2 0x01
357#define AQ_PHY_ADDR3 0x02
358#define AQ_PHY_ADDR4 0x03
Shaohui Xie8c7ce822016-01-28 15:38:15 +0800359#define AQR405_IRQ_MASK 0x36
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530360
361#define CONFIG_MII
Prabhakar Kushwaha0a95f8f2016-04-19 08:53:42 +0530362#define CONFIG_ETHPRIME "DPMAC1@xgmii"
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530363#define CONFIG_PHY_GIGE
Prabhakar Kushwaha7b3a6bc2015-06-28 11:03:59 +0530364#define CONFIG_PHY_AQUANTIA
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530365#endif
366
Saksham Jainc0c38d22016-03-23 16:24:35 +0530367#include <asm/fsl_secure_boot.h>
368
York Sune12abcb2015-03-20 19:28:24 -0700369#endif /* __LS2_RDB_H */