blob: d2cedfe860d47b5d68b0121aba4b348fcdcd0138 [file] [log] [blame]
Kumar Galae38209e2011-02-09 02:00:08 +00001/*
2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Galae38209e2011-02-09 02:00:08 +00005 */
6
7/*
8 * P5020 DS board configuration file
Scott Wooda1ef48c2012-08-14 10:14:51 +00009 * Also supports P5010 DS
Kumar Galae38209e2011-02-09 02:00:08 +000010 */
11#define CONFIG_P5020DS
Kumar Galae38209e2011-02-09 02:00:08 +000012#define CONFIG_PPC_P5020
13
Kumar Galad0af3b92011-08-31 09:50:13 -050014#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
15
16#define CONFIG_MMC
17#define CONFIG_NAND_FSL_ELBC
Zang Roy-R619112ce421a2012-11-26 00:05:38 +000018#define CONFIG_FSL_SATA_V2
Kumar Galad0af3b92011-08-31 09:50:13 -050019#define CONFIG_PCIE3
Kumar Galae38209e2011-02-09 02:00:08 +000020#define CONFIG_PCIE4
Kumar Gala9d8e8132011-09-10 10:44:13 -050021#define CONFIG_SYS_FSL_RAID_ENGINE
Kumar Gala4eb3c372011-10-14 13:28:52 -050022#define CONFIG_SYS_DPAA_RMAN
Kumar Galae38209e2011-02-09 02:00:08 +000023
Timur Tabi830b76f2012-10-05 09:48:53 +000024#define CONFIG_SYS_SRIO
25#define CONFIG_SRIO1 /* SRIO port 1 */
26#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gang27afb9c2013-05-07 16:30:46 +080027#define CONFIG_SRIO_PCIE_BOOT_MASTER
Kumar Galae38209e2011-02-09 02:00:08 +000028#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
29
30#include "corenet_ds.h"