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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Chin Liang See70fa4e72013-09-11 11:24:48 -05002/*
Ley Foon Tand5c5e3b2017-04-26 02:44:35 +08003 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
Chin Liang See70fa4e72013-09-11 11:24:48 -05004 */
5
Ley Foon Tand5c5e3b2017-04-26 02:44:35 +08006#ifndef _SYSTEM_MANAGER_H_
7#define _SYSTEM_MANAGER_H_
Chin Liang Seecca9f452013-12-30 18:26:14 -06008
Ley Foon Tan7cdb9122018-05-18 22:05:24 +08009#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
10#include <asm/arch/system_manager_s10.h>
11#else
Ley Foon Tanc3b49632017-04-26 02:44:40 +080012#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
13#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
14#define SYSMGR_ECC_OCRAM_EN BIT(0)
15#define SYSMGR_ECC_OCRAM_SERR BIT(3)
16#define SYSMGR_ECC_OCRAM_DERR BIT(4)
Marek Vasut61412722014-09-08 14:08:45 +020017#define SYSMGR_FPGAINTF_USEFPGA 0x1
Ley Foon Tanc3b49632017-04-26 02:44:40 +080018#define SYSMGR_FPGAINTF_SPIM0 BIT(0)
19#define SYSMGR_FPGAINTF_SPIM1 BIT(1)
20#define SYSMGR_FPGAINTF_EMAC0 BIT(2)
21#define SYSMGR_FPGAINTF_EMAC1 BIT(3)
22#define SYSMGR_FPGAINTF_NAND BIT(4)
23#define SYSMGR_FPGAINTF_SDMMC BIT(5)
Marek Vasut61412722014-09-08 14:08:45 +020024
Dinh Nguyenc4b66c42015-12-02 13:31:33 -060025#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
Marek Vasut61412722014-09-08 14:08:45 +020026
Pavel Machek57d75eb2014-09-08 14:08:45 +020027/* EMAC Group Bit definitions */
28#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
29#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
30#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
31
32#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
33#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
34#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
35
Ley Foon Tanc3b49632017-04-26 02:44:40 +080036/* For dedicated IO configuration */
37/* Voltage select enums */
38#define VOLTAGE_SEL_3V 0x0
39#define VOLTAGE_SEL_1P8V 0x1
40#define VOLTAGE_SEL_2P5V 0x2
41
42/* Input buffer enable */
43#define INPUT_BUF_DISABLE 0
44#define INPUT_BUF_1P8V 1
45#define INPUT_BUF_2P5V3V 2
46
47/* Weak pull up enable */
48#define WK_PU_DISABLE 0
49#define WK_PU_ENABLE 1
50
51/* Pull up slew rate control */
52#define PU_SLW_RT_SLOW 0
53#define PU_SLW_RT_FAST 1
54#define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW
55
56/* Pull down slew rate control */
57#define PD_SLW_RT_SLOW 0
58#define PD_SLW_RT_FAST 1
59#define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW
60
61/* Drive strength control */
62#define PU_DRV_STRG_DEFAULT 0x10
63#define PD_DRV_STRG_DEFAULT 0x10
64
65/* bit position */
66#define PD_DRV_STRG_LSB 0
67#define PD_SLW_RT_LSB 5
68#define PU_DRV_STRG_LSB 8
69#define PU_SLW_RT_LSB 13
70#define WK_PU_LSB 16
71#define INPUT_BUF_LSB 17
72#define BIAS_TRIM_LSB 19
73#define VOLTAGE_SEL_LSB 0
74
75#define ALT_SYSMGR_NOC_H2F_SET_MSK BIT(0)
76#define ALT_SYSMGR_NOC_LWH2F_SET_MSK BIT(4)
77#define ALT_SYSMGR_NOC_F2H_SET_MSK BIT(8)
78#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK BIT(16)
79#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK BIT(20)
80#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK BIT(24)
81#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK BIT(0)
82
83#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK BIT(1)
84#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK BIT(1)
85
Ley Foon Tand5c5e3b2017-04-26 02:44:35 +080086#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
87#include <asm/arch/system_manager_gen5.h>
Ley Foon Tanc3b49632017-04-26 02:44:40 +080088#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
89#include <asm/arch/system_manager_arria10.h>
Ley Foon Tand5c5e3b2017-04-26 02:44:35 +080090#endif
91
92#define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
93 (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
Ley Foon Tan7cdb9122018-05-18 22:05:24 +080094#endif
Chin Liang See70fa4e72013-09-11 11:24:48 -050095#endif /* _SYSTEM_MANAGER_H_ */