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Stefan Roesefdf21b12007-03-21 13:39:57 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/************************************************************************
25 * acadia.h - configuration for AMCC Acadia (405EZ)
26 ***********************************************************************/
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*-----------------------------------------------------------------------
32 * High Level Configuration Options
33 *----------------------------------------------------------------------*/
Stefan Roesef6c7b762007-03-24 15:45:34 +010034#define CONFIG_ACADIA 1 /* Board is Acadia */
35#define CONFIG_4xx 1 /* ... PPC4xx family */
36#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
Stefan Roesed4c0b702008-06-06 15:55:03 +020037
38/*
39 * Include common defines/options for all AMCC eval boards
40 */
41#define CONFIG_HOSTNAME acadia
42#include "amcc-common.h"
43
Stefan Roesed2f223e2007-05-24 08:22:09 +020044/* Detect Acadia PLL input clock automatically via CPLD bit */
45#define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
46 66666666 : 33333000)
Stefan Roesefdf21b12007-03-21 13:39:57 +010047
Stefan Roesef6c7b762007-03-24 15:45:34 +010048#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
49#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
Stefan Roesefdf21b12007-03-21 13:39:57 +010050
51#define CONFIG_NO_SERIAL_EEPROM
52/*#undef CONFIG_NO_SERIAL_EEPROM*/
53
54#ifdef CONFIG_NO_SERIAL_EEPROM
Stefan Roesefdf21b12007-03-21 13:39:57 +010055/*----------------------------------------------------------------------------
56 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
57 * assuming a 66MHz input clock to the 405EZ.
58 *---------------------------------------------------------------------------*/
59/* #define PLLMR0_100_100_12 */
60#define PLLMR0_200_133_66
61/* #define PLLMR0_266_160_80 */
62/* #define PLLMR0_333_166_83 */
63#endif
64
65/*-----------------------------------------------------------------------
66 * Base addresses -- Note these are effective addresses where the
67 * actual resources get mapped (not physical addresses)
68 *----------------------------------------------------------------------*/
Stefan Roesef6c7b762007-03-24 15:45:34 +010069#define CFG_FLASH_BASE 0xfe000000
Stefan Roesef6c7b762007-03-24 15:45:34 +010070#define CFG_CPLD_BASE 0x80000000
71#define CFG_NAND_ADDR 0xd0000000
Stefan Roesefdf21b12007-03-21 13:39:57 +010072#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
73
Stefan Roesef6c7b762007-03-24 15:45:34 +010074/*-----------------------------------------------------------------------
75 * Initial RAM & stack pointer
76 *----------------------------------------------------------------------*/
77#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */
78
79/* On Chip Memory location */
Stefan Roese80d99a42007-06-19 16:42:31 +020080#define CFG_OCM_DATA_ADDR 0xf8000000
Stefan Roesef6c7b762007-03-24 15:45:34 +010081#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
82#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
83#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
84
85#define CFG_GBL_DATA_SIZE 128 /* size for initial data */
86#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
87#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
88
89/*-----------------------------------------------------------------------
90 * Serial Port
91 *----------------------------------------------------------------------*/
92#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
93#define CFG_BASE_BAUD 691200
Stefan Roesef6c7b762007-03-24 15:45:34 +010094
95/*-----------------------------------------------------------------------
96 * Environment
97 *----------------------------------------------------------------------*/
Stefan Roesefdf21b12007-03-21 13:39:57 +010098#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Stefan Roesef6c7b762007-03-24 15:45:34 +010099#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roesefdf21b12007-03-21 13:39:57 +0100100#else
Stefan Roesef6c7b762007-03-24 15:45:34 +0100101#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
102#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
Stefan Roesefdf21b12007-03-21 13:39:57 +0100103#endif
104
Stefan Roesef6c7b762007-03-24 15:45:34 +0100105/*-----------------------------------------------------------------------
106 * FLASH related
107 *----------------------------------------------------------------------*/
Stefan Roese23d8d342007-06-06 11:42:13 +0200108#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Stefan Roesef6c7b762007-03-24 15:45:34 +0100109#define CFG_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200110#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roesef6c7b762007-03-24 15:45:34 +0100111
112#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
113#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
114#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
115
116#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
117#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
118
119#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
120#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
121
Stefan Roese23d8d342007-06-06 11:42:13 +0200122#else
123#define CFG_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */
Stefan Roese23d8d342007-06-06 11:42:13 +0200124#endif
125
Stefan Roesef6c7b762007-03-24 15:45:34 +0100126#ifdef CFG_ENV_IS_IN_FLASH
127#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
128#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
129#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
130
131/* Address and size of Redundant Environment Sector */
132#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
133#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
134#endif
135
Stefan Roese23d8d342007-06-06 11:42:13 +0200136/*
137 * IPL (Initial Program Loader, integrated inside CPU)
138 * Will load first 4k from NAND (SPL) into cache and execute it from there.
139 *
140 * SPL (Secondary Program Loader)
141 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
142 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
143 * controller and the NAND controller so that the special U-Boot image can be
144 * loaded from NAND to SDRAM.
145 *
146 * NUB (NAND U-Boot)
147 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
148 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
149 *
150 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
151 * set up. While still running from cache, I experienced problems accessing
152 * the NAND controller. sr - 2006-08-25
153 */
154#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
155#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
Stefan Roese80d99a42007-06-19 16:42:31 +0200156#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
Stefan Roese23d8d342007-06-06 11:42:13 +0200157#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
158#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
159#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
160
161/*
162 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
163 */
164#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
165#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
166
167/*
168 * Now the NAND chip has to be defined (no autodetection used!)
169 */
170#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
171#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
172#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
173#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
174#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
175
176#define CFG_NAND_ECCSIZE 256
177#define CFG_NAND_ECCBYTES 3
178#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
179#define CFG_NAND_OOBSIZE 16
180#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
181#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
182
183#ifdef CFG_ENV_IS_IN_NAND
184/*
185 * For NAND booting the environment is embedded in the U-Boot image. Please take
186 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
187 */
188#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
189#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
190#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
191#endif
192
Stefan Roesef6c7b762007-03-24 15:45:34 +0100193/*-----------------------------------------------------------------------
194 * RAM (CRAM)
195 *----------------------------------------------------------------------*/
196#define CFG_MBYTES_RAM 64 /* 64MB */
197
198/*-----------------------------------------------------------------------
199 * I2C
200 *----------------------------------------------------------------------*/
Stefan Roesef6c7b762007-03-24 15:45:34 +0100201#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
Stefan Roesef6c7b762007-03-24 15:45:34 +0100202
203#define CFG_I2C_MULTI_EEPROMS
204#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
205#define CFG_I2C_EEPROM_ADDR_LEN 1
206#define CFG_EEPROM_PAGE_WRITE_ENABLE
207#define CFG_EEPROM_PAGE_WRITE_BITS 3
208#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
209
210/* I2C SYSMON (LM75, AD7414 is almost compatible) */
211#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
212#define CONFIG_DTT_AD7414 1 /* use AD7414 */
213#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
214#define CFG_DTT_MAX_TEMP 70
215#define CFG_DTT_LOW_TEMP -30
216#define CFG_DTT_HYSTERESIS 3
217
Stefan Roesef6c7b762007-03-24 15:45:34 +0100218/*-----------------------------------------------------------------------
219 * Ethernet
220 *----------------------------------------------------------------------*/
Stefan Roesef6c7b762007-03-24 15:45:34 +0100221#define CONFIG_PHY_ADDR 0 /* PHY address */
Stefan Roese7efa49e2008-05-08 10:48:58 +0200222#define CONFIG_HAS_ETH0 1
Stefan Roesef6c7b762007-03-24 15:45:34 +0100223
Stefan Roesed4c0b702008-06-06 15:55:03 +0200224/*
225 * Default environment variables
226 */
Stefan Roesefdf21b12007-03-21 13:39:57 +0100227#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roesed4c0b702008-06-06 15:55:03 +0200228 CONFIG_AMCC_DEF_ENV \
229 CONFIG_AMCC_DEF_ENV_PPC \
230 CONFIG_AMCC_DEF_ENV_NOR_UPD \
231 CONFIG_AMCC_DEF_ENV_NAND_UPD \
Stefan Roesefdf21b12007-03-21 13:39:57 +0100232 "kernel_addr=fff10000\0" \
233 "ramdisk_addr=fff20000\0" \
Stefan Roesefdf21b12007-03-21 13:39:57 +0100234 "kozio=bootm ffc60000\0" \
235 ""
Stefan Roesefdf21b12007-03-21 13:39:57 +0100236
Stefan Roesefdf21b12007-03-21 13:39:57 +0100237#define CONFIG_USB_OHCI
238#define CONFIG_USB_STORAGE
239
Stefan Roesefdf21b12007-03-21 13:39:57 +0100240/* Partitions */
241#define CONFIG_MAC_PARTITION
242#define CONFIG_DOS_PARTITION
243#define CONFIG_ISO_PARTITION
244
245#define CONFIG_SUPPORT_VFAT
246
Jon Loeligerc5707f52007-07-04 22:31:42 -0500247/*
Stefan Roesed4c0b702008-06-06 15:55:03 +0200248 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500249 */
Jon Loeligerc5707f52007-07-04 22:31:42 -0500250#define CONFIG_CMD_DTT
Jon Loeligerc5707f52007-07-04 22:31:42 -0500251#define CONFIG_CMD_NAND
Jon Loeligerc5707f52007-07-04 22:31:42 -0500252#define CONFIG_CMD_USB
253
254/*
255 * No NOR on Acadia when NAND-booting
256 */
257#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
258#undef CONFIG_CMD_FLASH
259#undef CONFIG_CMD_IMLS
260#endif
261
Stefan Roesefdf21b12007-03-21 13:39:57 +0100262/*-----------------------------------------------------------------------
263 * NAND FLASH
264 *----------------------------------------------------------------------*/
265#define CFG_MAX_NAND_DEVICE 1
266#define NAND_MAX_CHIPS 1
Stefan Roesef6c7b762007-03-24 15:45:34 +0100267#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
Stefan Roesefdf21b12007-03-21 13:39:57 +0100268#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roesefdf21b12007-03-21 13:39:57 +0100269
270/*-----------------------------------------------------------------------
Stefan Roesefdf21b12007-03-21 13:39:57 +0100271 * External Bus Controller (EBC) Setup
Stefan Roesef6c7b762007-03-24 15:45:34 +0100272 *----------------------------------------------------------------------*/
Stefan Roese23d8d342007-06-06 11:42:13 +0200273#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
274#define CFG_NAND_CS 3
Stefan Roesef6c7b762007-03-24 15:45:34 +0100275/* Memory Bank 0 (Flash) initialization */
Stefan Roesefdf21b12007-03-21 13:39:57 +0100276#define CFG_EBC_PB0AP 0x03337200
Stefan Roesef6c7b762007-03-24 15:45:34 +0100277#define CFG_EBC_PB0CR 0xfe0bc000
Stefan Roesefdf21b12007-03-21 13:39:57 +0100278
Stefan Roese23d8d342007-06-06 11:42:13 +0200279/* Memory Bank 3 (NAND-FLASH) initialization */
280#define CFG_EBC_PB3AP 0x018003c0
281#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
282
Stefan Roesef6c7b762007-03-24 15:45:34 +0100283/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
284/* Memory Bank 1 (CRAM) initialization */
Stefan Roesefdf21b12007-03-21 13:39:57 +0100285#define CFG_EBC_PB1AP 0x030400c0
286#define CFG_EBC_PB1CR 0x000bc000
287
Stefan Roesef6c7b762007-03-24 15:45:34 +0100288/* Memory Bank 2 (CRAM) initialization */
Stefan Roesefdf21b12007-03-21 13:39:57 +0100289#define CFG_EBC_PB2AP 0x030400c0
290#define CFG_EBC_PB2CR 0x020bc000
Stefan Roese23d8d342007-06-06 11:42:13 +0200291#else
292#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
293/* Memory Bank 0 (NAND-FLASH) initialization */
294#define CFG_EBC_PB0AP 0x018003c0
295#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
Stefan Roesefdf21b12007-03-21 13:39:57 +0100296
Stefan Roese23d8d342007-06-06 11:42:13 +0200297/*
298 * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
299 * NAND-SPL already initialized the CRAM and EBC to sync mode.
300 */
301/* Memory Bank 1 (CRAM) initialization */
302#define CFG_EBC_PB1AP 0x9C0201C0
303#define CFG_EBC_PB1CR 0x000bc000
304
305/* Memory Bank 2 (CRAM) initialization */
306#define CFG_EBC_PB2AP 0x9C0201C0
307#define CFG_EBC_PB2CR 0x020bc000
308#endif
Stefan Roesefdf21b12007-03-21 13:39:57 +0100309
Stefan Roesef6c7b762007-03-24 15:45:34 +0100310/* Memory Bank 4 (CPLD) initialization */
Stefan Roesefdf21b12007-03-21 13:39:57 +0100311#define CFG_EBC_PB4AP 0x04006000
Stefan Roesef6c7b762007-03-24 15:45:34 +0100312#define CFG_EBC_PB4CR (CFG_CPLD_BASE | 0x18000)
Stefan Roesefdf21b12007-03-21 13:39:57 +0100313
314#define CFG_EBC_CFG 0xf8400000
315
316/*-----------------------------------------------------------------------
Stefan Roesef6c7b762007-03-24 15:45:34 +0100317 * GPIO Setup
318 *----------------------------------------------------------------------*/
319#define CFG_GPIO_CRAM_CLK 8
Stefan Roese23d8d342007-06-06 11:42:13 +0200320#define CFG_GPIO_CRAM_WAIT 9 /* GPIO-In */
Stefan Roesef6c7b762007-03-24 15:45:34 +0100321#define CFG_GPIO_CRAM_ADV 10
Stefan Roese23d8d342007-06-06 11:42:13 +0200322#define CFG_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
Stefan Roesef6c7b762007-03-24 15:45:34 +0100323
324/*-----------------------------------------------------------------------
Stefan Roesefdf21b12007-03-21 13:39:57 +0100325 * Definitions for GPIO_0 setup (PPC405EZ specific)
326 *
Stefan Roesed2f223e2007-05-24 08:22:09 +0200327 * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
328 * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
Stefan Roesefdf21b12007-03-21 13:39:57 +0100329 * GPIO0[4] - External Bus Controller Hold Input
330 * GPIO0[5] - External Bus Controller Priority Input
331 * GPIO0[6] - External Bus Controller HLDA Output
332 * GPIO0[7] - External Bus Controller Bus Request Output
333 * GPIO0[8] - CRAM Clk Output
334 * GPIO0[9] - External Bus Controller Ready Input
335 * GPIO0[10] - CRAM Adv Output
336 * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
337 * GPIO0[25] - External DMA Request Input
338 * GPIO0[26] - External DMA EOT I/O
339 * GPIO0[25] - External DMA Ack_n Output
340 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
341 * GPIO0[28-30] - Trace Outputs / PWM Inputs
342 * GPIO0[31] - PWM_8 I/O
343 */
Stefan Roese23d8d342007-06-06 11:42:13 +0200344#define CFG_GPIO0_TCR 0xC0A00000
345#define CFG_GPIO0_OSRL 0x50004400
Stefan Roesed2f223e2007-05-24 08:22:09 +0200346#define CFG_GPIO0_OSRH 0x02000055
Stefan Roese23d8d342007-06-06 11:42:13 +0200347#define CFG_GPIO0_ISR1L 0x00001000
Stefan Roesefdf21b12007-03-21 13:39:57 +0100348#define CFG_GPIO0_ISR1H 0x00000055
Stefan Roesed2f223e2007-05-24 08:22:09 +0200349#define CFG_GPIO0_TSRL 0x02000000
Stefan Roesefdf21b12007-03-21 13:39:57 +0100350#define CFG_GPIO0_TSRH 0x00000055
351
352/*-----------------------------------------------------------------------
353 * Definitions for GPIO_1 setup (PPC405EZ specific)
354 *
355 * GPIO1[0-6] - PWM_9 to PWM_15 I/O
356 * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
357 * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
358 * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
359 * GPIO1[10-12] - UART0 Control Inputs
360 * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
361 * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
362 * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
363 * GPIO1[16] - SPI_SS_1_N Output
364 * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
365 */
Stefan Roese23d8d342007-06-06 11:42:13 +0200366#define CFG_GPIO1_TCR 0xFFFF8414
Stefan Roesefdf21b12007-03-21 13:39:57 +0100367#define CFG_GPIO1_OSRL 0x40000110
Stefan Roese23d8d342007-06-06 11:42:13 +0200368#define CFG_GPIO1_OSRH 0x55455555
Stefan Roesefdf21b12007-03-21 13:39:57 +0100369#define CFG_GPIO1_ISR1L 0x15555445
Stefan Roese23d8d342007-06-06 11:42:13 +0200370#define CFG_GPIO1_ISR1H 0x00000000
Stefan Roesefdf21b12007-03-21 13:39:57 +0100371#define CFG_GPIO1_TSRL 0x00000000
Stefan Roese23d8d342007-06-06 11:42:13 +0200372#define CFG_GPIO1_TSRH 0x00000000
Stefan Roesefdf21b12007-03-21 13:39:57 +0100373
Stefan Roesefdf21b12007-03-21 13:39:57 +0100374#endif /* __CONFIG_H */