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T Karthik Reddy73701e72022-05-12 04:05:32 -06001// SPDX-License-Identifier: GPL-2.0
2/*
3 * (C) Copyright 2018 Xilinx
4 *
5 * Cadence QSPI controller DMA operations
6 */
7
8#include <clk.h>
T Karthik Reddy73701e72022-05-12 04:05:32 -06009#include <memalign.h>
10#include <wait_bit.h>
11#include <asm/io.h>
12#include <asm/gpio.h>
13#include <asm/cache.h>
14#include <cpu_func.h>
15#include <zynqmp_firmware.h>
16#include <asm/arch/hardware.h>
17#include "cadence_qspi.h"
18#include <dt-bindings/power/xlnx-versal-power.h>
19
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060020int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
T Karthik Reddy73701e72022-05-12 04:05:32 -060021 const struct spi_mem_op *op)
22{
23 u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data;
24 u8 opcode, addr_bytes, *rxbuf, dummy_cycles;
25
26 n_rx = op->data.nbytes;
27 rxbuf = op->data.buf.in;
28 rx_rem = n_rx % 4;
29 bytes_to_dma = n_rx - rx_rem;
30
31 if (bytes_to_dma) {
T Karthik Reddy3b49fbf2022-05-12 04:05:34 -060032 cadence_qspi_apb_enable_linear_mode(false);
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060033 reg = readl(priv->regbase + CQSPI_REG_CONFIG);
T Karthik Reddy73701e72022-05-12 04:05:32 -060034 reg |= CQSPI_REG_CONFIG_ENBL_DMA;
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060035 writel(reg, priv->regbase + CQSPI_REG_CONFIG);
T Karthik Reddy73701e72022-05-12 04:05:32 -060036
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060037 writel(bytes_to_dma, priv->regbase + CQSPI_REG_INDIRECTRDBYTES);
T Karthik Reddy73701e72022-05-12 04:05:32 -060038
39 writel(CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE,
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060040 priv->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE);
T Karthik Reddy73701e72022-05-12 04:05:32 -060041 writel(CQSPI_DFLT_DMA_PERIPH_CFG,
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060042 priv->regbase + CQSPI_REG_DMA_PERIPH_CFG);
Venkatesh Yadav Abbarapucf014982023-10-11 08:45:15 +053043 writel(lower_32_bits((unsigned long)rxbuf), priv->regbase +
T Karthik Reddy73701e72022-05-12 04:05:32 -060044 CQSPI_DMA_DST_ADDR_REG);
Venkatesh Yadav Abbarapucf014982023-10-11 08:45:15 +053045 writel(upper_32_bits((unsigned long)rxbuf), priv->regbase +
46 CQSPI_DMA_DST_ADDR_MSB_REG);
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060047 writel(priv->trigger_address, priv->regbase +
T Karthik Reddy73701e72022-05-12 04:05:32 -060048 CQSPI_DMA_SRC_RD_ADDR_REG);
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060049 writel(bytes_to_dma, priv->regbase +
T Karthik Reddy73701e72022-05-12 04:05:32 -060050 CQSPI_DMA_DST_SIZE_REG);
51 flush_dcache_range((unsigned long)rxbuf,
52 (unsigned long)rxbuf + bytes_to_dma);
53 writel(CQSPI_DFLT_DST_CTRL_REG_VAL,
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060054 priv->regbase + CQSPI_DMA_DST_CTRL_REG);
T Karthik Reddy73701e72022-05-12 04:05:32 -060055
56 /* Start the indirect read transfer */
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060057 writel(CQSPI_REG_INDIRECTRD_START, priv->regbase +
T Karthik Reddy73701e72022-05-12 04:05:32 -060058 CQSPI_REG_INDIRECTRD);
59 /* Wait for dma to complete transfer */
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060060 ret = cadence_qspi_apb_wait_for_dma_cmplt(priv);
T Karthik Reddy73701e72022-05-12 04:05:32 -060061 if (ret)
62 return ret;
63
64 /* Clear indirect completion status */
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060065 writel(CQSPI_REG_INDIRECTRD_DONE, priv->regbase +
T Karthik Reddy73701e72022-05-12 04:05:32 -060066 CQSPI_REG_INDIRECTRD);
67 rxbuf += bytes_to_dma;
68 }
69
70 if (rx_rem) {
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060071 reg = readl(priv->regbase + CQSPI_REG_CONFIG);
T Karthik Reddy73701e72022-05-12 04:05:32 -060072 reg &= ~CQSPI_REG_CONFIG_ENBL_DMA;
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060073 writel(reg, priv->regbase + CQSPI_REG_CONFIG);
T Karthik Reddy73701e72022-05-12 04:05:32 -060074
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060075 reg = readl(priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
T Karthik Reddy73701e72022-05-12 04:05:32 -060076 reg += bytes_to_dma;
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060077 writel(reg, priv->regbase + CQSPI_REG_CMDADDRESS);
T Karthik Reddy73701e72022-05-12 04:05:32 -060078
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060079 addr_bytes = readl(priv->regbase + CQSPI_REG_SIZE) &
T Karthik Reddy73701e72022-05-12 04:05:32 -060080 CQSPI_REG_SIZE_ADDRESS_MASK;
81
82 opcode = CMD_4BYTE_FAST_READ;
83 dummy_cycles = 8;
84 writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode,
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060085 priv->regbase + CQSPI_REG_RD_INSTR);
T Karthik Reddy73701e72022-05-12 04:05:32 -060086
87 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
88 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
89 reg |= (addr_bytes & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
90 CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
91 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060092 dummy_cycles = (readl(priv->regbase + CQSPI_REG_RD_INSTR) >>
T Karthik Reddy73701e72022-05-12 04:05:32 -060093 CQSPI_REG_RD_INSTR_DUMMY_LSB) &
94 CQSPI_REG_RD_INSTR_DUMMY_MASK;
95 reg |= (dummy_cycles & CQSPI_REG_CMDCTRL_DUMMY_MASK) <<
96 CQSPI_REG_CMDCTRL_DUMMY_LSB;
97 reg |= (((rx_rem - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) <<
98 CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
Ashok Reddy Somaf5817652022-08-24 05:38:47 -060099 ret = cadence_qspi_apb_exec_flash_cmd(priv->regbase, reg);
T Karthik Reddy73701e72022-05-12 04:05:32 -0600100 if (ret)
101 return ret;
102
Ashok Reddy Somaf5817652022-08-24 05:38:47 -0600103 data = readl(priv->regbase + CQSPI_REG_CMDREADDATALOWER);
T Karthik Reddy73701e72022-05-12 04:05:32 -0600104 memcpy(rxbuf, &data, rx_rem);
105 }
106
107 return 0;
108}
109
Ashok Reddy Somaf5817652022-08-24 05:38:47 -0600110int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv)
T Karthik Reddy73701e72022-05-12 04:05:32 -0600111{
112 u32 timeout = CQSPI_DMA_TIMEOUT;
113
Ashok Reddy Somaf5817652022-08-24 05:38:47 -0600114 while (!(readl(priv->regbase + CQSPI_DMA_DST_I_STS_REG) &
T Karthik Reddy73701e72022-05-12 04:05:32 -0600115 CQSPI_DMA_DST_I_STS_DONE) && timeout--)
116 udelay(1);
117
118 if (!timeout) {
119 printf("DMA timeout\n");
120 return -ETIMEDOUT;
121 }
122
Ashok Reddy Somaf5817652022-08-24 05:38:47 -0600123 writel(readl(priv->regbase + CQSPI_DMA_DST_I_STS_REG),
124 priv->regbase + CQSPI_DMA_DST_I_STS_REG);
T Karthik Reddy73701e72022-05-12 04:05:32 -0600125 return 0;
126}
T Karthik Reddy3d71b2d2022-05-12 04:05:33 -0600127
Venkatesh Yadav Abbarapubbb87a72024-11-08 12:05:37 +0530128#if !CONFIG_IS_ENABLED(DM_GPIO)
129int cadence_qspi_flash_reset(struct udevice *dev)
T Karthik Reddy3d71b2d2022-05-12 04:05:33 -0600130{
131 /* CRP WPROT */
132 writel(0, WPROT_CRP);
133 /* GPIO Reset */
134 writel(0, RST_GPIO);
135
136 /* disable IOU write protection */
137 writel(0, WPROT_LPD_MIO);
138
139 /* set direction as output */
140 writel((readl(BOOT_MODE_DIR) | BIT(FLASH_RESET_GPIO)),
Ashok Reddy Soma8a456eb2022-11-16 07:11:54 -0700141 BOOT_MODE_DIR);
T Karthik Reddy3d71b2d2022-05-12 04:05:33 -0600142
143 /* Data output enable */
144 writel((readl(BOOT_MODE_OUT) | BIT(FLASH_RESET_GPIO)),
Ashok Reddy Soma8a456eb2022-11-16 07:11:54 -0700145 BOOT_MODE_OUT);
T Karthik Reddy3d71b2d2022-05-12 04:05:33 -0600146
147 /* IOU SLCR write enable */
148 writel(0, WPROT_PMC_MIO);
149
150 /* set MIO as GPIO */
151 writel(0x60, MIO_PIN_12);
152
153 /* Set value 1 to pin */
154 writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
155 udelay(10);
156
157 /* Disable Tri-state */
158 writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI);
159 udelay(1);
160
161 /* Set value 0 to pin */
162 writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
163 udelay(10);
164
165 /* Set value 1 to pin */
166 writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
167 udelay(10);
168
169 return 0;
170}
171#endif
T Karthik Reddy3b49fbf2022-05-12 04:05:34 -0600172
173void cadence_qspi_apb_enable_linear_mode(bool enable)
174{
Simon Glassf65db342023-02-05 15:44:33 -0700175 if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
T Karthik Reddy3b49fbf2022-05-12 04:05:34 -0600176 if (enable)
177 /* ahb read mode */
178 xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI,
179 IOCTL_OSPI_MUX_SELECT,
180 PM_OSPI_MUX_SEL_LINEAR, 0, NULL);
181 else
182 /* DMA mode */
183 xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI,
184 IOCTL_OSPI_MUX_SELECT,
185 PM_OSPI_MUX_SEL_DMA, 0, NULL);
186 } else {
187 if (enable)
188 writel(readl(VERSAL_AXI_MUX_SEL) |
189 VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
190 else
191 writel(readl(VERSAL_AXI_MUX_SEL) &
192 ~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
193 }
194}