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git01.mediatek.com / filogic / uboot / 22b08aa947c6c8c20654001a78ced5cf6e6936ff / . / drivers / ata / dwc_ahsata.c
blob: 2695bef22204450cf8a05bb54c96d314afafe5df [file] [log] [blame]
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Terry Lv <r65388@freescale.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]6 */
7
Simon Glass602cedc2017-07-29 11:35:08 -0600[diff] [blame]8#include <common.h>
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]9#include <ahci.h>
10#include <fis.h>
Simon Glass602cedc2017-07-29 11:35:08 -0600[diff] [blame]11#include <libata.h>
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]12#include <malloc.h>
Simon Glass602cedc2017-07-29 11:35:08 -0600[diff] [blame]13#include <sata.h>
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]14#include <asm/io.h>
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]15#include <asm/arch/clock.h>
Tim Harveye9d13472014-05-07 22:23:35 -0700[diff] [blame]16#include <asm/arch/sys_proto.h>
Simon Glass602cedc2017-07-29 11:35:08 -0600[diff] [blame]17#include <linux/bitops.h>
18#include <linux/ctype.h>
19#include <linux/errno.h>
Simon Glass7b2a6292017-07-29 11:35:09 -0600[diff] [blame]20#include "dwc_ahsata_priv.h"
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]21
22struct sata_port_regs {
23 u32 clb;
24 u32 clbu;
25 u32 fb;
26 u32 fbu;
27 u32 is;
28 u32 ie;
29 u32 cmd;
30 u32 res1[1];
31 u32 tfd;
32 u32 sig;
33 u32 ssts;
34 u32 sctl;
35 u32 serr;
36 u32 sact;
37 u32 ci;
38 u32 sntf;
39 u32 res2[1];
40 u32 dmacr;
41 u32 res3[1];
42 u32 phycr;
43 u32 physr;
44};
45
46struct sata_host_regs {
47 u32 cap;
48 u32 ghc;
49 u32 is;
50 u32 pi;
51 u32 vs;
52 u32 ccc_ctl;
53 u32 ccc_ports;
54 u32 res1[2];
55 u32 cap2;
56 u32 res2[30];
57 u32 bistafr;
58 u32 bistcr;
59 u32 bistfctr;
60 u32 bistsr;
61 u32 bistdecr;
62 u32 res3[2];
63 u32 oobr;
64 u32 res4[8];
65 u32 timer1ms;
66 u32 res5[1];
67 u32 gparam1r;
68 u32 gparam2r;
69 u32 pparamr;
70 u32 testr;
71 u32 versionr;
72 u32 idr;
73};
74
75#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
76#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
77
78#define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
79
Tang Yuantian3f262d02015-07-09 14:37:30 +0800[diff] [blame]80static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]81{
82 return base + 0x100 + (port * 0x80);
83}
84
85static int waiting_for_cmd_completed(u8 *offset,
86 int timeout_msec,
87 u32 sign)
88{
89 int i;
90 u32 status;
91
92 for (i = 0;
93 ((status = readl(offset)) & sign) && i < timeout_msec;
94 ++i)
95 mdelay(1);
96
97 return (i < timeout_msec) ? 0 : -1;
98}
99
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]100static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]101{
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]102 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]103
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]104 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
105 writel(0x02060b14, &host_mmio->oobr);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]106
107 return 0;
108}
109
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]110static int ahci_host_init(struct ahci_uc_priv *uc_priv)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]111{
112 u32 tmp, cap_save, num_ports;
113 int i, j, timeout = 1000;
114 struct sata_port_regs *port_mmio = NULL;
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]115 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]116 int clk = mxc_get_clock(MXC_SATA_CLK);
117
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]118 cap_save = readl(&host_mmio->cap);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]119 cap_save |= SATA_HOST_CAP_SSS;
120
121 /* global controller reset */
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]122 tmp = readl(&host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]123 if ((tmp & SATA_HOST_GHC_HR) == 0)
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]124 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]125
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]126 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]127 ;
128
129 if (timeout <= 0) {
130 debug("controller reset failed (0x%x)\n", tmp);
131 return -1;
132 }
133
134 /* Set timer 1ms */
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]135 writel(clk / 1000, &host_mmio->timer1ms);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]136
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]137 ahci_setup_oobr(uc_priv, 0);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]138
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]139 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
140 writel(cap_save, &host_mmio->cap);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]141 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]142 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]143
144 /*
145 * Determine which Ports are implemented by the DWC_ahsata,
146 * by reading the PI register. This bit map value aids the
147 * software to determine how many Ports are available and
148 * which Port registers need to be initialized.
149 */
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]150 uc_priv->cap = readl(&host_mmio->cap);
151 uc_priv->port_map = readl(&host_mmio->pi);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]152
153 /* Determine how many command slots the HBA supports */
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]154 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]155
156 debug("cap 0x%x port_map 0x%x n_ports %d\n",
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]157 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]158
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]159 for (i = 0; i < uc_priv->n_ports; i++) {
160 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]161 port_mmio = uc_priv->port[i].port_mmio;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]162
163 /* Ensure that the DWC_ahsata is in idle state */
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]164 tmp = readl(&port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]165
166 /*
167 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
168 * are all cleared, the Port is in an idle state.
169 */
170 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
171 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
172
173 /*
174 * System software places a Port into the idle state by
175 * clearing P#CMD.ST and waiting for P#CMD.CR to return
176 * 0 when read.
177 */
178 tmp &= ~SATA_PORT_CMD_ST;
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]179 writel_with_flush(tmp, &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]180
181 /*
182 * spec says 500 msecs for each bit, so
183 * this is slightly incorrect.
184 */
185 mdelay(500);
186
187 timeout = 1000;
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]188 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]189 && --timeout)
190 ;
191
192 if (timeout <= 0) {
193 debug("port reset failed (0x%x)\n", tmp);
194 return -1;
195 }
196 }
197
198 /* Spin-up device */
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]199 tmp = readl(&port_mmio->cmd);
200 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]201
202 /* Wait for spin-up to finish */
203 timeout = 1000;
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]204 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]205 && --timeout)
206 ;
207 if (timeout <= 0) {
208 debug("Spin-Up can't finish!\n");
209 return -1;
210 }
211
212 for (j = 0; j < 100; ++j) {
213 mdelay(10);
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]214 tmp = readl(&port_mmio->ssts);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]215 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
216 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
217 break;
218 }
219
220 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
221 timeout = 1000;
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]222 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]223 && --timeout)
224 ;
225 if (timeout <= 0) {
226 debug("Can't find DIAG_X set!\n");
227 return -1;
228 }
229
230 /*
231 * For each implemented Port, clear the P#SERR
232 * register, by writing ones to each implemented\
233 * bit location.
234 */
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]235 tmp = readl(&port_mmio->serr);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]236 debug("P#SERR 0x%x\n",
237 tmp);
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]238 writel(tmp, &port_mmio->serr);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]239
240 /* Ack any pending irq events for this port */
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]241 tmp = readl(&host_mmio->is);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]242 debug("IS 0x%x\n", tmp);
243 if (tmp)
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]244 writel(tmp, &host_mmio->is);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]245
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]246 writel(1 << i, &host_mmio->is);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]247
248 /* set irq mask (enables interrupts) */
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]249 writel(DEF_PORT_IRQ, &port_mmio->ie);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]250
251 /* register linkup ports */
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]252 tmp = readl(&port_mmio->ssts);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]253 debug("Port %d status: 0x%x\n", i, tmp);
254 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]255 uc_priv->link_port_map |= (0x01 << i);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]256 }
257
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]258 tmp = readl(&host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]259 debug("GHC 0x%x\n", tmp);
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]260 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
261 tmp = readl(&host_mmio->ghc);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]262 debug("GHC 0x%x\n", tmp);
263
264 return 0;
265}
266
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]267static void ahci_print_info(struct ahci_uc_priv *uc_priv)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]268{
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]269 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]270 u32 vers, cap, impl, speed;
271 const char *speed_s;
272 const char *scc_s;
273
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]274 vers = readl(&host_mmio->vs);
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]275 cap = uc_priv->cap;
276 impl = uc_priv->port_map;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]277
278 speed = (cap & SATA_HOST_CAP_ISS_MASK)
279 >> SATA_HOST_CAP_ISS_OFFSET;
280 if (speed == 1)
281 speed_s = "1.5";
282 else if (speed == 2)
283 speed_s = "3";
284 else
285 speed_s = "?";
286
287 scc_s = "SATA";
288
289 printf("AHCI %02x%02x.%02x%02x "
290 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
291 (vers >> 24) & 0xff,
292 (vers >> 16) & 0xff,
293 (vers >> 8) & 0xff,
294 vers & 0xff,
295 ((cap >> 8) & 0x1f) + 1,
296 (cap & 0x1f) + 1,
297 speed_s,
298 impl,
299 scc_s);
300
301 printf("flags: "
302 "%s%s%s%s%s%s"
303 "%s%s%s%s%s%s%s\n",
304 cap & (1 << 31) ? "64bit " : "",
305 cap & (1 << 30) ? "ncq " : "",
306 cap & (1 << 28) ? "ilck " : "",
307 cap & (1 << 27) ? "stag " : "",
308 cap & (1 << 26) ? "pm " : "",
309 cap & (1 << 25) ? "led " : "",
310 cap & (1 << 24) ? "clo " : "",
311 cap & (1 << 19) ? "nz " : "",
312 cap & (1 << 18) ? "only " : "",
313 cap & (1 << 17) ? "pmp " : "",
314 cap & (1 << 15) ? "pio " : "",
315 cap & (1 << 14) ? "slum " : "",
316 cap & (1 << 13) ? "part " : "");
317}
318
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]319static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
320 unsigned char *buf, int buf_len)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]321{
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]322 struct ahci_ioports *pp = &uc_priv->port[port];
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]323 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
324 u32 sg_count, max_bytes;
325 int i;
326
327 max_bytes = MAX_DATA_BYTES_PER_SG;
328 sg_count = ((buf_len - 1) / max_bytes) + 1;
329 if (sg_count > AHCI_MAX_SG) {
330 printf("Error:Too much sg!\n");
331 return -1;
332 }
333
334 for (i = 0; i < sg_count; i++) {
335 ahci_sg->addr =
336 cpu_to_le32((u32)buf + i * max_bytes);
337 ahci_sg->addr_hi = 0;
338 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
339 (buf_len < max_bytes
340 ? (buf_len - 1)
341 : (max_bytes - 1)));
342 ahci_sg++;
343 buf_len -= max_bytes;
344 }
345
346 return sg_count;
347}
348
349static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
350{
351 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
352 AHCI_CMD_SLOT_SZ * cmd_slot);
353
354 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
355 cmd_hdr->opts = cpu_to_le32(opts);
356 cmd_hdr->status = 0;
Tang Yuantian3f262d02015-07-09 14:37:30 +0800[diff] [blame]357 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
358#ifdef CONFIG_PHYS_64BIT
359 pp->cmd_slot->tbl_addr_hi =
360 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
361#endif
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]362}
363
364#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
365
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]366static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
367 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
368 s32 is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]369{
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]370 struct ahci_ioports *pp = &uc_priv->port[port];
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]371 struct sata_port_regs *port_mmio = pp->port_mmio;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]372 u32 opts;
373 int sg_count = 0, cmd_slot = 0;
374
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]375 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]376 if (32 == cmd_slot) {
377 printf("Can't find empty command slot!\n");
378 return 0;
379 }
380
381 /* Check xfer length */
382 if (buf_len > MAX_BYTES_PER_TRANS) {
383 printf("Max transfer length is %dB\n\r",
384 MAX_BYTES_PER_TRANS);
385 return 0;
386 }
387
388 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
389 if (buf && buf_len)
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]390 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]391 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]392 if (is_write) {
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]393 opts |= 0x40;
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]394 flush_cache((ulong)buf, buf_len);
395 }
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]396 ahci_fill_cmd_slot(pp, cmd_slot, opts);
397
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]398 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]399 writel_with_flush(1 << cmd_slot, &port_mmio->ci);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]400
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]401 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
402 0x1 << cmd_slot)) {
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]403 printf("timeout exit!\n");
404 return -1;
405 }
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]406 invalidate_dcache_range((int)(pp->cmd_slot),
407 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]408 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
409 pp->cmd_slot->status);
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]410 if (!is_write)
411 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]412
413 return buf_len;
414}
415
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]416static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]417{
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]418 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
419 struct sata_fis_h2d *cfis = &h2d;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]420
421 memset(cfis, 0, sizeof(struct sata_fis_h2d));
422 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
423 cfis->pm_port_c = 1 << 7;
424 cfis->command = ATA_CMD_SET_FEATURES;
425 cfis->features = SETFEATURES_XFER;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]426 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]427
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]428 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]429}
430
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]431static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]432{
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]433 struct ahci_ioports *pp = &uc_priv->port[port];
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]434 struct sata_port_regs *port_mmio = pp->port_mmio;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]435 u32 port_status;
436 u32 mem;
437 int timeout = 10000000;
438
439 debug("Enter start port: %d\n", port);
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]440 port_status = readl(&port_mmio->ssts);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]441 debug("Port %d status: %x\n", port, port_status);
442 if ((port_status & 0xf) != 0x03) {
443 printf("No Link on this port!\n");
444 return -1;
445 }
446
447 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
448 if (!mem) {
449 free(pp);
450 printf("No mem for table!\n");
451 return -ENOMEM;
452 }
453
454 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
455 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
456
457 /*
458 * First item in chunk of DMA memory: 32-slot command table,
459 * 32 bytes each in size
460 */
461 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
462 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
463 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
464
465 /*
466 * Second item: Received-FIS area, 256-Byte aligned
467 */
468 pp->rx_fis = mem;
469 mem += AHCI_RX_FIS_SZ;
470
471 /*
472 * Third item: data area for storing a single command
473 * and its scatter-gather table
474 */
475 pp->cmd_tbl = mem;
Tang Yuantian3f262d02015-07-09 14:37:30 +0800[diff] [blame]476 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]477
478 mem += AHCI_CMD_TBL_HDR;
479
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]480 writel_with_flush(0x00004444, &port_mmio->dmacr);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]481 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]482 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
483 writel_with_flush(pp->rx_fis, &port_mmio->fb);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]484
485 /* Enable FRE */
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]486 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
487 &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]488
489 /* Wait device ready */
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]490 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]491 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
492 && --timeout)
493 ;
494 if (timeout <= 0) {
495 debug("Device not ready for BSY, DRQ and"
496 "ERR in TFD!\n");
497 return -1;
498 }
499
500 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
501 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]502 PORT_CMD_START, &port_mmio->cmd);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]503
504 debug("Exit start port %d\n", port);
505
506 return 0;
507}
508
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]509static void dwc_ahsata_print_info(struct blk_desc *pdev)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]510{
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]511 printf("SATA Device Info:\n\r");
512#ifdef CONFIG_SYS_64BIT_LBA
513 printf("S/N: %s\n\rProduct model number: %s\n\r"
514 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
515 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
516#else
517 printf("S/N: %s\n\rProduct model number: %s\n\r"
518 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
519 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
520#endif
521}
522
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]523static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]524{
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]525 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
526 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]527 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]528
529 memset(cfis, 0, sizeof(struct sata_fis_h2d));
530
531 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
532 cfis->pm_port_c = 0x80; /* is command */
533 cfis->command = ATA_CMD_ID_ATA;
534
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]535 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
536 READ_CMD);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]537 ata_swap_buf_le16(id, ATA_ID_WORDS);
538}
539
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]540static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]541{
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]542 uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
543 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
544 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]545}
546
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]547static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
548 u32 blkcnt, u8 *buffer, int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]549{
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]550 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
551 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]552 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]553 u32 block;
554
555 block = start;
556
557 memset(cfis, 0, sizeof(struct sata_fis_h2d));
558
559 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
560 cfis->pm_port_c = 0x80; /* is command */
561 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
562 cfis->device = ATA_LBA;
563
564 cfis->device |= (block >> 24) & 0xf;
565 cfis->lba_high = (block >> 16) & 0xff;
566 cfis->lba_mid = (block >> 8) & 0xff;
567 cfis->lba_low = block & 0xff;
568 cfis->sector_count = (u8)(blkcnt & 0xff);
569
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]570 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
571 ATA_SECT_SIZE * blkcnt, is_write) > 0)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]572 return blkcnt;
573 else
574 return 0;
575}
576
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]577static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]578{
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]579 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
580 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]581 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]582
583 memset(cfis, 0, sizeof(struct sata_fis_h2d));
584
585 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
586 cfis->pm_port_c = 0x80; /* is command */
587 cfis->command = ATA_CMD_FLUSH;
588
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]589 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]590}
591
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]592static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
593 lbaint_t blkcnt, u8 *buffer, int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]594{
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]595 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
596 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]597 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]598 u64 block;
599
600 block = (u64)start;
601
602 memset(cfis, 0, sizeof(struct sata_fis_h2d));
603
604 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
605 cfis->pm_port_c = 0x80; /* is command */
606
607 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
608 : ATA_CMD_READ_EXT;
609
610 cfis->lba_high_exp = (block >> 40) & 0xff;
611 cfis->lba_mid_exp = (block >> 32) & 0xff;
612 cfis->lba_low_exp = (block >> 24) & 0xff;
613 cfis->lba_high = (block >> 16) & 0xff;
614 cfis->lba_mid = (block >> 8) & 0xff;
615 cfis->lba_low = block & 0xff;
616 cfis->device = ATA_LBA;
617 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
618 cfis->sector_count = blkcnt & 0xff;
619
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]620 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
621 ATA_SECT_SIZE * blkcnt, is_write) > 0)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]622 return blkcnt;
623 else
624 return 0;
625}
626
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]627static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]628{
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]629 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
630 struct sata_fis_h2d *cfis = &h2d;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]631 u8 port = uc_priv->hard_port_no;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]632
633 memset(cfis, 0, sizeof(struct sata_fis_h2d));
634
635 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
636 cfis->pm_port_c = 0x80; /* is command */
637 cfis->command = ATA_CMD_FLUSH_EXT;
638
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]639 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]640}
641
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]642static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]643{
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]644 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]645 uc_priv->flags |= SATA_FLAG_WCACHE;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]646 if (ata_id_has_flush(id))
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]647 uc_priv->flags |= SATA_FLAG_FLUSH;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]648 if (ata_id_has_flush_ext(id))
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]649 uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]650}
651
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]652static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
653 lbaint_t blkcnt, const void *buffer,
654 int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]655{
656 u32 start, blks;
657 u8 *addr;
658 int max_blks;
659
660 start = blknr;
661 blks = blkcnt;
662 addr = (u8 *)buffer;
663
664 max_blks = ATA_MAX_SECTORS_LBA48;
665
666 do {
667 if (blks > max_blks) {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]668 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
669 max_blks, addr,
670 is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]671 return 0;
672 start += max_blks;
673 blks -= max_blks;
674 addr += ATA_SECT_SIZE * max_blks;
675 } else {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]676 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
677 addr, is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]678 return 0;
679 start += blks;
680 blks = 0;
681 addr += ATA_SECT_SIZE * blks;
682 }
683 } while (blks != 0);
684
685 return blkcnt;
686}
687
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]688static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
689 lbaint_t blkcnt, const void *buffer,
690 int is_write)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]691{
692 u32 start, blks;
693 u8 *addr;
694 int max_blks;
695
696 start = blknr;
697 blks = blkcnt;
698 addr = (u8 *)buffer;
699
700 max_blks = ATA_MAX_SECTORS;
701 do {
702 if (blks > max_blks) {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]703 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
704 max_blks, addr,
705 is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]706 return 0;
707 start += max_blks;
708 blks -= max_blks;
709 addr += ATA_SECT_SIZE * max_blks;
710 } else {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]711 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
712 addr, is_write))
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]713 return 0;
714 start += blks;
715 blks = 0;
716 addr += ATA_SECT_SIZE * blks;
717 }
718 } while (blks != 0);
719
720 return blkcnt;
721}
722
Simon Glass22b08aa2017-07-29 11:35:11 -0600[diff] [blame^]723static int ahci_init_one(int pdev)
724{
725 int rc;
726 struct ahci_uc_priv *uc_priv = NULL;
727
728 uc_priv = malloc(sizeof(struct ahci_uc_priv));
729 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
730 uc_priv->dev = pdev;
731
732 uc_priv->host_flags = ATA_FLAG_SATA
733 | ATA_FLAG_NO_LEGACY
734 | ATA_FLAG_MMIO
735 | ATA_FLAG_PIO_DMA
736 | ATA_FLAG_NO_ATAPI;
737
738 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
739
740 /* initialize adapter */
741 rc = ahci_host_init(uc_priv);
742 if (rc)
743 goto err_out;
744
745 ahci_print_info(uc_priv);
746
747 /* Save the uc_private struct to block device struct */
748 sata_dev_desc[pdev].priv = uc_priv;
749
750 return 0;
751
752err_out:
753 return rc;
754}
755
Simon Glassed82fcc2017-07-29 11:35:03 -0600[diff] [blame]756int init_sata(int dev)
757{
758 int i;
759 u32 linkmap;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]760 struct ahci_uc_priv *uc_priv = NULL;
Simon Glassed82fcc2017-07-29 11:35:03 -0600[diff] [blame]761
762#if defined(CONFIG_MX6)
763 if (!is_mx6dq() && !is_mx6dqp())
764 return 1;
765#endif
766 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
767 printf("The sata index %d is out of ranges\n\r", dev);
768 return -1;
769 }
770
771 ahci_init_one(dev);
772
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]773 uc_priv = sata_dev_desc[dev].priv;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]774 linkmap = uc_priv->link_port_map;
Simon Glassed82fcc2017-07-29 11:35:03 -0600[diff] [blame]775
776 if (0 == linkmap) {
777 printf("No port device detected!\n");
778 return 1;
779 }
780
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]781 for (i = 0; i < uc_priv->n_ports; i++) {
Simon Glassed82fcc2017-07-29 11:35:03 -0600[diff] [blame]782 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]783 if (ahci_port_start(uc_priv, (u8)i)) {
Simon Glassed82fcc2017-07-29 11:35:03 -0600[diff] [blame]784 printf("Can not start port %d\n", i);
785 return 1;
786 }
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]787 uc_priv->hard_port_no = i;
Simon Glassed82fcc2017-07-29 11:35:03 -0600[diff] [blame]788 break;
789 }
790 }
791
792 return 0;
793}
794
795int reset_sata(int dev)
796{
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]797 struct ahci_uc_priv *uc_priv;
Simon Glassed82fcc2017-07-29 11:35:03 -0600[diff] [blame]798 struct sata_host_regs *host_mmio;
799
800 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
801 printf("The sata index %d is out of ranges\n\r", dev);
802 return -1;
803 }
804
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]805 uc_priv = sata_dev_desc[dev].priv;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]806 if (NULL == uc_priv)
Simon Glassed82fcc2017-07-29 11:35:03 -0600[diff] [blame]807 /* not initialized, so nothing to reset */
808 return 0;
809
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]810 host_mmio = uc_priv->mmio_base;
Simon Glassed82fcc2017-07-29 11:35:03 -0600[diff] [blame]811 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
812 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
813 udelay(100);
814
815 return 0;
816}
817
Nikita Kiryanov66914042014-08-20 15:08:53 +0300[diff] [blame]818int sata_port_status(int dev, int port)
819{
820 struct sata_port_regs *port_mmio;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]821 struct ahci_uc_priv *uc_priv = NULL;
Nikita Kiryanov66914042014-08-20 15:08:53 +0300[diff] [blame]822
823 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
824 return -EINVAL;
825
826 if (sata_dev_desc[dev].priv == NULL)
827 return -ENODEV;
828
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]829 uc_priv = sata_dev_desc[dev].priv;
830 port_mmio = uc_priv->port[port].port_mmio;
Nikita Kiryanov66914042014-08-20 15:08:53 +0300[diff] [blame]831
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]832 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
Nikita Kiryanov66914042014-08-20 15:08:53 +0300[diff] [blame]833}
834
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]835/*
836 * SATA interface between low level driver and command layer
837 */
Tom Rini532e8672012-09-29 07:53:06 -0700[diff] [blame]838ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]839{
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]840 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]841 u32 rc;
842
843 if (sata_dev_desc[dev].lba48)
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]844 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt,
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]845 buffer, READ_CMD);
846 else
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]847 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt,
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]848 buffer, READ_CMD);
849 return rc;
850}
851
Tom Rini532e8672012-09-29 07:53:06 -0700[diff] [blame]852ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]853{
854 u32 rc;
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]855 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]856 u32 flags = uc_priv->flags;
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]857
858 if (sata_dev_desc[dev].lba48) {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]859 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
860 WRITE_CMD);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]861 if ((flags & SATA_FLAG_WCACHE) &&
862 (flags & SATA_FLAG_FLUSH_EXT))
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]863 dwc_ahsata_flush_cache_ext(uc_priv);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]864 } else {
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]865 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
866 WRITE_CMD);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]867 if ((flags & SATA_FLAG_WCACHE) &&
868 (flags & SATA_FLAG_FLUSH))
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]869 dwc_ahsata_flush_cache(uc_priv);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]870 }
871 return rc;
872}
873
874int scan_sata(int dev)
875{
876 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
877 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
878 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
879 u16 *id;
880 u64 n_sectors;
Simon Glassd30e76c2017-07-29 11:35:05 -0600[diff] [blame]881 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]882 u8 port = uc_priv->hard_port_no;
Simon Glass96f2af42017-07-29 11:35:07 -0600[diff] [blame]883 struct blk_desc *pdev = &sata_dev_desc[dev];
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]884
Eric Nelson998816b2013-06-15 16:09:55 -0700[diff] [blame]885 id = (u16 *)memalign(ARCH_DMA_MINALIGN,
886 roundup(ARCH_DMA_MINALIGN,
887 (ATA_ID_WORDS * 2)));
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]888 if (!id) {
889 printf("id malloc failed\n\r");
890 return -1;
891 }
892
893 /* Identify device to get information */
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]894 dwc_ahsata_identify(uc_priv, id);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]895
896 /* Serial number */
897 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
898 memcpy(pdev->product, serial, sizeof(serial));
899
900 /* Firmware version */
901 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
902 memcpy(pdev->revision, firmware, sizeof(firmware));
903
904 /* Product model */
905 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
906 memcpy(pdev->vendor, product, sizeof(product));
907
908 /* Totoal sectors */
909 n_sectors = ata_id_n_sectors(id);
910 pdev->lba = (u32)n_sectors;
911
912 pdev->type = DEV_TYPE_HARDDISK;
913 pdev->blksz = ATA_SECT_SIZE;
914 pdev->lun = 0 ;
915
916 /* Check if support LBA48 */
917 if (ata_id_has_lba48(id)) {
918 pdev->lba48 = 1;
919 debug("Device support LBA48\n\r");
920 }
921
922 /* Get the NCQ queue depth from device */
Simon Glassb1f7f582017-07-29 11:35:04 -0600[diff] [blame]923 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
924 uc_priv->flags |= ata_id_queue_depth(id);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]925
926 /* Get the xfer mode from device */
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]927 dwc_ahsata_xfer_mode(uc_priv, id);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]928
929 /* Get the write cache status from device */
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]930 dwc_ahsata_init_wcache(uc_priv, id);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]931
932 /* Set the xfer mode to highest speed */
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]933 ahci_set_feature(uc_priv, port);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]934
935 free((void *)id);
936
Simon Glassc5fc2a32017-07-29 11:35:06 -0600[diff] [blame]937 dwc_ahsata_print_info(&sata_dev_desc[dev]);
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]938
Stefano Babic771bfd12012-02-22 00:24:39 +0000[diff] [blame]939 return 0;
940}