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git01.mediatek.com / filogic / uboot / f8621460c62e7c3ed58f90fdf889da918224187a / . / arch / arm / dts / imx8mp-verdin.dtsi
blob: 68100a17263f78c28573c1e2fe4b21952af63731 [file] [log] [blame]
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include "dt-bindings/pwm/pwm.h"
7#include "imx8mp.dtsi"
8
9/ {
10 chosen {
11 stdout-path = &uart3;
12 };
13
14 aliases {
15 /* Ethernet aliases to ensure correct MAC addresses */
16 ethernet0 = &eqos;
17 ethernet1 = &fec;
18 rtc0 = &rtc_i2c;
19 rtc1 = &snvs_rtc;
20 };
21
22 backlight: backlight {
23 compatible = "pwm-backlight";
24 brightness-levels = <0 45 63 88 119 158 203 255>;
25 default-brightness-level = <4>;
26 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
27 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
30 power-supply = <&reg_3p3v>;
31 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
32 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
33 status = "disabled";
34 };
35
36 backlight_mezzanine: backlight-mezzanine {
37 compatible = "pwm-backlight";
38 brightness-levels = <0 45 63 88 119 158 203 255>;
39 default-brightness-level = <4>;
40 /* Verdin GPIO 4 (SODIMM 212) */
41 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
42 /* Verdin PWM_2 (SODIMM 16) */
43 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
44 status = "disabled";
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_gpio_keys>;
51
52 wakeup {
53 debounce-interval = <10>;
54 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
55 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
56 label = "Wake-Up";
57 linux,code = <KEY_WAKEUP>;
58 wakeup-source;
59 };
60 };
61
62 /* Carrier Board Supplies */
63 reg_1p8v: regulator-1p8v {
64 compatible = "regulator-fixed";
65 regulator-max-microvolt = <1800000>;
66 regulator-min-microvolt = <1800000>;
67 regulator-name = "+V1.8_SW";
68 };
69
70 reg_3p3v: regulator-3p3v {
71 compatible = "regulator-fixed";
72 regulator-max-microvolt = <3300000>;
73 regulator-min-microvolt = <3300000>;
74 regulator-name = "+V3.3_SW";
75 };
76
77 reg_5p0v: regulator-5p0v {
78 compatible = "regulator-fixed";
79 regulator-max-microvolt = <5000000>;
80 regulator-min-microvolt = <5000000>;
81 regulator-name = "+V5_SW";
82 };
83
84 /* Non PMIC On-module Supplies */
85 reg_module_eth1phy: regulator-module-eth1phy {
86 compatible = "regulator-fixed";
87 enable-active-high;
88 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
89 off-on-delay = <500000>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_reg_eth>;
92 regulator-always-on;
93 regulator-boot-on;
94 regulator-max-microvolt = <3300000>;
95 regulator-min-microvolt = <3300000>;
96 regulator-name = "On-module +V3.3_ETH";
97 startup-delay-us = <200000>;
98 vin-supply = <&reg_vdd_3v3>;
99 };
100
101 reg_usb1_vbus: regulator-usb1-vbus {
102 compatible = "regulator-fixed";
103 enable-active-high;
104 /* Verdin USB_1_EN (SODIMM 155) */
105 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_usb1_vbus>;
108 regulator-max-microvolt = <5000000>;
109 regulator-min-microvolt = <5000000>;
110 regulator-name = "USB_1_EN";
111 };
112
113 reg_usb2_vbus: regulator-usb2-vbus {
114 compatible = "regulator-fixed";
115 enable-active-high;
116 /* Verdin USB_2_EN (SODIMM 185) */
117 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_usb2_vbus>;
120 regulator-max-microvolt = <5000000>;
121 regulator-min-microvolt = <5000000>;
122 regulator-name = "USB_2_EN";
123 };
124
125 reg_usdhc2_vmmc: regulator-usdhc2 {
126 compatible = "regulator-fixed";
127 enable-active-high;
128 /* Verdin SD_1_PWR_EN (SODIMM 76) */
129 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
130 off-on-delay = <100000>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
133 regulator-max-microvolt = <3300000>;
134 regulator-min-microvolt = <3300000>;
135 regulator-name = "+V3.3_SD";
136 startup-delay-us = <2000>;
137 };
138
139 reserved-memory {
140 #address-cells = <2>;
141 #size-cells = <2>;
142 ranges;
143
144 /* Use the kernel configuration settings instead */
145 /delete-node/ linux,cma;
146 };
147};
148
149/* Verdin SPI_1 */
150&ecspi1 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_ecspi1>;
156};
157
158/* Verdin ETH_1 (On-module PHY) */
159&eqos {
160 phy-handle = <&ethphy0>;
161 phy-mode = "rgmii-id";
162 phy-supply = <&reg_module_eth1phy>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_eqos>;
165 snps,force_thresh_dma_mode;
166 snps,mtl-rx-config = <&mtl_rx_setup>;
167 snps,mtl-tx-config = <&mtl_tx_setup>;
168
169 mdio {
170 compatible = "snps,dwmac-mdio";
171 #address-cells = <1>;
172 #size-cells = <0>;
173
174 ethphy0: ethernet-phy@7 {
175 compatible = "ethernet-phy-ieee802.3-c22";
176 eee-broken-100tx;
177 eee-broken-1000t;
178 interrupt-parent = <&gpio1>;
179 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
180 micrel,led-mode = <0>;
181 reg = <7>;
182 };
183 };
184
185 mtl_rx_setup: rx-queues-config {
186 snps,rx-queues-to-use = <5>;
187 snps,rx-sched-sp;
188
189 queue0 {
190 snps,dcb-algorithm;
191 snps,priority = <0x1>;
192 snps,map-to-dma-channel = <0>;
193 };
194
195 queue1 {
196 snps,dcb-algorithm;
197 snps,priority = <0x2>;
198 snps,map-to-dma-channel = <1>;
199 };
200
201 queue2 {
202 snps,dcb-algorithm;
203 snps,priority = <0x4>;
204 snps,map-to-dma-channel = <2>;
205 };
206
207 queue3 {
208 snps,dcb-algorithm;
209 snps,priority = <0x8>;
210 snps,map-to-dma-channel = <3>;
211 };
212
213 queue4 {
214 snps,dcb-algorithm;
215 snps,priority = <0xf0>;
216 snps,map-to-dma-channel = <4>;
217 };
218 };
219
220 mtl_tx_setup: tx-queues-config {
221 snps,tx-queues-to-use = <5>;
222 snps,tx-sched-sp;
223
224 queue0 {
225 snps,dcb-algorithm;
226 snps,priority = <0x1>;
227 };
228
229 queue1 {
230 snps,dcb-algorithm;
231 snps,priority = <0x2>;
232 };
233
234 queue2 {
235 snps,dcb-algorithm;
236 snps,priority = <0x4>;
237 };
238
239 queue3 {
240 snps,dcb-algorithm;
241 snps,priority = <0x8>;
242 };
243
244 queue4 {
245 snps,dcb-algorithm;
246 snps,priority = <0xf0>;
247 };
248 };
249};
250
251/* Verdin ETH_2_RGMII */
252&fec {
253 fsl,magic-packet;
254 phy-handle = <&ethphy1>;
255 phy-mode = "rgmii-id";
256 pinctrl-names = "default", "sleep";
257 pinctrl-0 = <&pinctrl_fec>;
258 pinctrl-1 = <&pinctrl_fec_sleep>;
259
260 mdio {
261 #address-cells = <1>;
262 #size-cells = <0>;
263
264 ethphy1: ethernet-phy@7 {
265 compatible = "ethernet-phy-ieee802.3-c22";
266 interrupt-parent = <&gpio4>;
267 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
268 micrel,led-mode = <0>;
269 reg = <7>;
270 };
271 };
272};
273
274/* Verdin CAN_1 */
275&flexcan1 {
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_flexcan1>;
278 status = "disabled";
279};
280
281/* Verdin CAN_2 */
282&flexcan2 {
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_flexcan2>;
285 status = "disabled";
286};
287
288/* Verdin QSPI_1 */
289&flexspi {
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_flexspi0>;
292};
293
294&gpio1 {
295 gpio-line-names = "SODIMM_206",
296 "SODIMM_208",
297 "",
298 "",
299 "",
300 "SODIMM_210",
301 "SODIMM_212",
302 "SODIMM_216",
303 "SODIMM_218",
304 "",
305 "",
306 "SODIMM_16",
307 "SODIMM_155",
308 "SODIMM_157",
309 "SODIMM_185",
310 "SODIMM_91";
311};
312
313&gpio2 {
314 gpio-line-names = "",
315 "",
316 "",
317 "",
318 "",
319 "",
320 "SODIMM_143",
321 "SODIMM_141",
322 "",
323 "",
324 "SODIMM_161",
325 "",
326 "SODIMM_84",
327 "SODIMM_78",
328 "SODIMM_74",
329 "SODIMM_80",
330 "SODIMM_82",
331 "SODIMM_70",
332 "SODIMM_72";
333
334 ctrl-sleep-moci-hog {
335 gpio-hog;
336 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
337 gpios = <29 GPIO_ACTIVE_HIGH>;
338 line-name = "CTRL_SLEEP_MOCI#";
339 output-high;
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
342 };
343};
344
345&gpio3 {
346 gpio-line-names = "SODIMM_52",
347 "SODIMM_54",
348 "",
349 "",
350 "",
351 "",
352 "SODIMM_56",
353 "SODIMM_58",
354 "SODIMM_60",
355 "SODIMM_62",
356 "",
357 "",
358 "",
359 "",
360 "SODIMM_66",
361 "",
362 "SODIMM_64",
363 "",
364 "",
365 "SODIMM_34",
366 "SODIMM_19",
367 "",
368 "SODIMM_32",
369 "",
370 "",
371 "SODIMM_30",
372 "SODIMM_59",
373 "SODIMM_57",
374 "SODIMM_63",
375 "SODIMM_61";
376};
377
378&gpio4 {
379 gpio-line-names = "SODIMM_252",
380 "SODIMM_222",
381 "SODIMM_36",
382 "SODIMM_220",
383 "SODIMM_193",
384 "SODIMM_191",
385 "SODIMM_201",
386 "SODIMM_203",
387 "SODIMM_205",
388 "SODIMM_207",
389 "SODIMM_199",
390 "SODIMM_197",
391 "SODIMM_221",
392 "SODIMM_219",
393 "SODIMM_217",
394 "SODIMM_215",
395 "SODIMM_211",
396 "SODIMM_213",
397 "SODIMM_189",
398 "SODIMM_244",
399 "SODIMM_38",
400 "",
401 "SODIMM_76",
402 "SODIMM_135",
403 "SODIMM_133",
404 "SODIMM_17",
405 "SODIMM_24",
406 "SODIMM_26",
407 "SODIMM_21",
408 "SODIMM_256",
409 "SODIMM_48",
410 "SODIMM_44";
411};
412
413/* On-module I2C */
414&i2c1 {
415 clock-frequency = <400000>;
416 pinctrl-names = "default", "gpio";
417 pinctrl-0 = <&pinctrl_i2c1>;
418 pinctrl-1 = <&pinctrl_i2c1_gpio>;
419 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
420 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
421 status = "okay";
422
423 pca9450: pmic@25 {
424 compatible = "nxp,pca9450c";
425 interrupt-parent = <&gpio1>;
426 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
427 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_pmic>;
430 reg = <0x25>;
431 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
432
433 /*
434 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
435 * I2C level shifter for the TLA2024 ADC behind this PMIC.
436 */
437
438 regulators {
439 BUCK1 {
440 regulator-always-on;
441 regulator-boot-on;
442 regulator-max-microvolt = <1000000>;
443 regulator-min-microvolt = <720000>;
444 regulator-name = "On-module +VDD_SOC (BUCK1)";
445 regulator-ramp-delay = <3125>;
446 };
447
448 BUCK2 {
449 nxp,dvs-run-voltage = <950000>;
450 nxp,dvs-standby-voltage = <850000>;
451 regulator-always-on;
452 regulator-boot-on;
453 regulator-max-microvolt = <1025000>;
454 regulator-min-microvolt = <720000>;
455 regulator-name = "On-module +VDD_ARM (BUCK2)";
456 regulator-ramp-delay = <3125>;
457 };
458
459 reg_vdd_3v3: BUCK4 {
460 regulator-always-on;
461 regulator-boot-on;
462 regulator-max-microvolt = <3300000>;
463 regulator-min-microvolt = <3300000>;
464 regulator-name = "On-module +V3.3 (BUCK4)";
465 };
466
467 reg_vdd_1v8: BUCK5 {
468 regulator-always-on;
469 regulator-boot-on;
470 regulator-max-microvolt = <1800000>;
471 regulator-min-microvolt = <1800000>;
472 regulator-name = "PWR_1V8_MOCI (BUCK5)";
473 };
474
475 BUCK6 {
476 regulator-always-on;
477 regulator-boot-on;
478 regulator-max-microvolt = <1155000>;
479 regulator-min-microvolt = <1045000>;
480 regulator-name = "On-module +VDD_DDR (BUCK6)";
481 };
482
483 LDO1 {
484 regulator-always-on;
485 regulator-boot-on;
486 regulator-max-microvolt = <1950000>;
487 regulator-min-microvolt = <1650000>;
488 regulator-name = "On-module +V1.8_SNVS (LDO1)";
489 };
490
491 LDO2 {
492 regulator-always-on;
493 regulator-boot-on;
494 regulator-max-microvolt = <1150000>;
495 regulator-min-microvolt = <800000>;
496 regulator-name = "On-module +V0.8_SNVS (LDO2)";
497 };
498
499 LDO3 {
500 regulator-always-on;
501 regulator-boot-on;
502 regulator-max-microvolt = <1800000>;
503 regulator-min-microvolt = <1800000>;
504 regulator-name = "On-module +V1.8A (LDO3)";
505 };
506
507 LDO4 {
508 regulator-always-on;
509 regulator-boot-on;
510 regulator-max-microvolt = <3300000>;
511 regulator-min-microvolt = <3300000>;
512 regulator-name = "On-module +V3.3_ADC (LDO4)";
513 };
514
515 LDO5 {
516 regulator-max-microvolt = <3300000>;
517 regulator-min-microvolt = <1800000>;
518 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
519 };
520 };
521 };
522
523 rtc_i2c: rtc@32 {
524 compatible = "epson,rx8130";
525 reg = <0x32>;
526 };
527
528 /* On-module temperature sensor */
529 hwmon_temp_module: sensor@48 {
530 compatible = "ti,tmp1075";
531 reg = <0x48>;
532 vs-supply = <&reg_vdd_1v8>;
533 };
534
535 adc@49 {
536 compatible = "ti,ads1015";
537 reg = <0x49>;
538 #address-cells = <1>;
539 #size-cells = <0>;
540
541 /* Verdin I2C_1 (ADC_4 - ADC_3) */
542 channel@0 {
543 reg = <0>;
544 ti,datarate = <4>;
545 ti,gain = <2>;
546 };
547
548 /* Verdin I2C_1 (ADC_4 - ADC_1) */
549 channel@1 {
550 reg = <1>;
551 ti,datarate = <4>;
552 ti,gain = <2>;
553 };
554
555 /* Verdin I2C_1 (ADC_3 - ADC_1) */
556 channel@2 {
557 reg = <2>;
558 ti,datarate = <4>;
559 ti,gain = <2>;
560 };
561
562 /* Verdin I2C_1 (ADC_2 - ADC_1) */
563 channel@3 {
564 reg = <3>;
565 ti,datarate = <4>;
566 ti,gain = <2>;
567 };
568
569 /* Verdin I2C_1 ADC_4 */
570 channel@4 {
571 reg = <4>;
572 ti,datarate = <4>;
573 ti,gain = <2>;
574 };
575
576 /* Verdin I2C_1 ADC_3 */
577 channel@5 {
578 reg = <5>;
579 ti,datarate = <4>;
580 ti,gain = <2>;
581 };
582
583 /* Verdin I2C_1 ADC_2 */
584 channel@6 {
585 reg = <6>;
586 ti,datarate = <4>;
587 ti,gain = <2>;
588 };
589
590 /* Verdin I2C_1 ADC_1 */
591 channel@7 {
592 reg = <7>;
593 ti,datarate = <4>;
594 ti,gain = <2>;
595 };
596 };
597
598 eeprom@50 {
599 compatible = "st,24c02";
600 pagesize = <16>;
601 reg = <0x50>;
602 };
603};
604
605/* Verdin I2C_2_DSI */
606&i2c2 {
607 /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */
608 clock-frequency = <10000>;
609 pinctrl-names = "default", "gpio";
610 pinctrl-0 = <&pinctrl_i2c2>;
611 pinctrl-1 = <&pinctrl_i2c2_gpio>;
612 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
613 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
614
615 atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
616 compatible = "atmel,maxtouch";
617 /* Verdin GPIO_3 (SODIMM 210) */
618 interrupt-parent = <&gpio1>;
619 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
620 reg = <0x4a>;
621 /* Verdin GPIO_2 (SODIMM 208) */
622 reset-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
623 status = "disabled";
624 };
625};
626
627/* TODO: Verdin I2C_3_HDMI */
628
629/* Verdin I2C_4_CSI */
630&i2c3 {
631 clock-frequency = <400000>;
632 pinctrl-names = "default", "gpio";
633 pinctrl-0 = <&pinctrl_i2c3>;
634 pinctrl-1 = <&pinctrl_i2c3_gpio>;
635 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
636 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
637};
638
639/* Verdin I2C_1 */
640&i2c4 {
641 clock-frequency = <400000>;
642 pinctrl-names = "default", "gpio";
643 pinctrl-0 = <&pinctrl_i2c4>;
644 pinctrl-1 = <&pinctrl_i2c4_gpio>;
645 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
646 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
647
648 gpio_expander_21: gpio-expander@21 {
649 compatible = "nxp,pcal6416";
650 #gpio-cells = <2>;
651 gpio-controller;
652 reg = <0x21>;
653 vcc-supply = <&reg_3p3v>;
654 status = "disabled";
655 };
656
657 lvds_ti_sn65dsi83: bridge@2c {
658 compatible = "ti,sn65dsi83";
659 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
660 /* Verdin GPIO_10_DSI (SODIMM 21) */
661 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
662 pinctrl-names = "default";
663 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
664 reg = <0x2c>;
665 status = "disabled";
666 };
667
668 /* Current measurement into module VCC */
669 hwmon: hwmon@40 {
670 compatible = "ti,ina219";
671 reg = <0x40>;
672 shunt-resistor = <10000>;
673 status = "disabled";
674 };
675
676 hdmi_lontium_lt8912: hdmi@48 {
677 compatible = "lontium,lt8912b";
678 pinctrl-names = "default";
679 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
680 reg = <0x48>;
681 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
682 /* Verdin GPIO_10_DSI (SODIMM 21) */
683 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
684 status = "disabled";
685 };
686
687 atmel_mxt_ts: touch@4a {
688 compatible = "atmel,maxtouch";
689 /*
690 * Verdin GPIO_9_DSI
691 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
692 */
693 interrupt-parent = <&gpio4>;
694 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
695 pinctrl-names = "default";
696 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
697 reg = <0x4a>;
698 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
699 reset-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
700 status = "disabled";
701 };
702
703 /* Temperature sensor on carrier board */
704 hwmon_temp: sensor@4f {
705 compatible = "ti,tmp75c";
706 reg = <0x4f>;
707 status = "disabled";
708 };
709
710 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
711 eeprom_display_adapter: eeprom@50 {
712 compatible = "st,24c02";
713 pagesize = <16>;
714 reg = <0x50>;
715 status = "disabled";
716 };
717
718 /* EEPROM on carrier board */
719 eeprom_carrier_board: eeprom@57 {
720 compatible = "st,24c02";
721 pagesize = <16>;
722 reg = <0x57>;
723 status = "disabled";
724 };
725};
726
727/* TODO: Verdin PCIE_1 */
728
729/* Verdin PWM_1 */
730&pwm1 {
731 pinctrl-names = "default";
732 pinctrl-0 = <&pinctrl_pwm_1>;
733 #pwm-cells = <3>;
734};
735
736/* Verdin PWM_2 */
737&pwm2 {
738 pinctrl-names = "default";
739 pinctrl-0 = <&pinctrl_pwm_2>;
740 #pwm-cells = <3>;
741};
742
743/* Verdin PWM_3_DSI */
744&pwm3 {
745 pinctrl-names = "default";
746 pinctrl-0 = <&pinctrl_pwm_3>;
747 #pwm-cells = <3>;
748};
749
750/* TODO: Verdin I2S_1 */
751
752/* TODO: Verdin I2S_2 */
753
754&snvs_pwrkey {
755 status = "okay";
756};
757
758/* Verdin UART_1 */
759&uart1 {
760 pinctrl-names = "default";
761 pinctrl-0 = <&pinctrl_uart1>;
762 uart-has-rtscts;
763};
764
765/* Verdin UART_2 */
766&uart2 {
767 pinctrl-names = "default";
768 pinctrl-0 = <&pinctrl_uart2>;
769 uart-has-rtscts;
770};
771
772/* Verdin UART_3, used as the Linux Console */
773&uart3 {
774 pinctrl-names = "default";
775 pinctrl-0 = <&pinctrl_uart3>;
776};
777
778/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */
779&uart4 {
780 pinctrl-names = "default";
781 pinctrl-0 = <&pinctrl_uart4>;
782};
783
784/* Verdin USB_1 */
785&usb3_phy0 {
786 vbus-supply = <&reg_usb1_vbus>;
787};
788
789&usb_dwc3_0 {
790 adp-disable;
791 dr_mode = "otg";
792 hnp-disable;
793 maximum-speed = "high-speed";
794 over-current-active-low;
795 pinctrl-names = "default";
796 pinctrl-0 = <&pinctrl_usb_1_id>;
797 srp-disable;
798};
799
800/* Verdin USB_2 */
801&usb3_phy1 {
802 vbus-supply = <&reg_usb2_vbus>;
803};
804
805&usb_dwc3_1 {
806 disable-over-current;
807 dr_mode = "host";
808};
809
810/* Verdin SD_1 */
811&usdhc2 {
812 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
813 assigned-clock-rates = <400000000>;
814 bus-width = <4>;
815 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
816 disable-wp;
817 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
818 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
819 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
820 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
821 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
822 vmmc-supply = <&reg_usdhc2_vmmc>;
823};
824
825/* On-module eMMC */
826&usdhc3 {
827 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
828 assigned-clock-rates = <400000000>;
829 bus-width = <8>;
830 non-removable;
831 pinctrl-names = "default", "state_100mhz", "state_200mhz";
832 pinctrl-0 = <&pinctrl_usdhc3>;
833 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
834 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
835 status = "okay";
836};
837
838&wdog1 {
839 fsl,ext-reset-output;
840 pinctrl-names = "default";
841 pinctrl-0 = <&pinctrl_wdog>;
842 status = "okay";
843};
844
845&iomuxc {
846 pinctrl_bt_uart: btuartgrp {
847 fsl,pins =
848 <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>,
849 <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>,
850 <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>,
851 <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>;
852 };
853
854 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
855 fsl,pins =
856 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */
857 };
858
859 pinctrl_ecspi1: ecspi1grp {
860 fsl,pins =
861 <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */
862 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */
863 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */
864 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */
865 };
866
867 /* Connection On Board PHY */
868 pinctrl_eqos: eqosgrp {
869 fsl,pins =
870 <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>,
871 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>,
872 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>,
873 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>,
874 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>,
875 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>,
876 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>,
877 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>,
878 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>,
879 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>,
880 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>,
881 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>,
882 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>,
883 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>;
884 };
885
886 /* ETH_INT# shared with TPM_INT# (usually N/A) */
887 pinctrl_eth_tpm_int: ethtpmintgrp {
888 fsl,pins =
889 <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>;
890 };
891
892 /* Connection Carrier Board PHY ETH_2 */
893 pinctrl_fec: fecgrp {
894 fsl,pins =
895 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
896 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
897 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
898 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
899 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
900 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
901 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
902 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
903 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */
904 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */
905 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */
906 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */
907 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */
908 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */
909 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */
910 };
911
912 pinctrl_fec_sleep: fecsleepgrp {
913 fsl,pins =
914 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
915 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
916 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
917 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
918 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
919 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
920 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
921 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
922 <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */
923 <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */
924 <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */
925 <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */
926 <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */
927 <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */
928 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */
929 };
930
931 pinctrl_flexcan1: flexcan1grp {
932 fsl,pins =
933 <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */
934 <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */
935 };
936
937 pinctrl_flexcan2: flexcan2grp {
938 fsl,pins =
939 <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */
940 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */
941 };
942
943 pinctrl_flexspi0: flexspi0grp {
944 fsl,pins =
945 <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
946 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */
947 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */
948 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */
949 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */
950 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */
951 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */
952 <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */
953 };
954
955 pinctrl_gpio1: gpio1grp {
956 fsl,pins =
957 <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */
958 };
959
960 pinctrl_gpio2: gpio2grp {
961 fsl,pins =
962 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */
963 };
964
965 pinctrl_gpio3: gpio3grp {
966 fsl,pins =
967 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */
968 };
969
970 pinctrl_gpio4: gpio4grp {
971 fsl,pins =
972 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */
973 };
974
975 pinctrl_gpio5: gpio5grp {
976 fsl,pins =
977 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */
978 };
979
980 pinctrl_gpio6: gpio6grp {
981 fsl,pins =
982 <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */
983 };
984
985 pinctrl_gpio7: gpio7grp {
986 fsl,pins =
987 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */
988 };
989
990 pinctrl_gpio8: gpio8grp {
991 fsl,pins =
992 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */
993 };
994
995 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
996 pinctrl_gpio_9_dsi: gpio9dsigrp {
997 fsl,pins =
998 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */
999 };
1000
1001 /* Verdin GPIO_10_DSI */
1002 pinctrl_gpio_10_dsi: gpio10dsigrp {
1003 fsl,pins =
1004 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */
1005 };
1006
1007 /* Non-wifi MSP usage only */
1008 pinctrl_gpio_hog1: gpiohog1grp {
1009 fsl,pins =
1010 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */
1011 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */
1012 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */
1013 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */
1014 };
1015
1016 /* USB_2_OC# */
1017 pinctrl_gpio_hog2: gpiohog2grp {
1018 fsl,pins =
1019 <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */
1020 };
1021
1022 pinctrl_gpio_hog3: gpiohog3grp {
1023 fsl,pins =
1024 <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4>, /* SODIMM 157 */
1025 /* CSI_1_MCLK */
1026 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */
1027 };
1028
1029 /* Wifi usage only */
1030 pinctrl_gpio_hog4: gpiohog4grp {
1031 fsl,pins =
1032 <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */
1033 <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */
1034 };
1035
1036 pinctrl_gpio_keys: gpiokeysgrp {
1037 fsl,pins =
1038 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */
1039 };
1040
1041 pinctrl_hdmi_hog: hdmihoggrp {
1042 fsl,pins =
1043 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */
1044 <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */
1045 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */
1046 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */
1047 };
1048
1049 /* On-module I2C */
1050 pinctrl_i2c1: i2c1grp {
1051 fsl,pins =
1052 <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */
1053 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */
1054 };
1055
1056 pinctrl_i2c1_gpio: i2c1gpiogrp {
1057 fsl,pins =
1058 <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */
1059 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */
1060 };
1061
1062 /* Verdin I2C_2_DSI */
1063 pinctrl_i2c2: i2c2grp {
1064 fsl,pins =
1065 <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */
1066 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */
1067 };
1068
1069 pinctrl_i2c2_gpio: i2c2gpiogrp {
1070 fsl,pins =
1071 <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */
1072 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */
1073 };
1074
1075 /* Verdin I2C_4_CSI */
1076 pinctrl_i2c3: i2c3grp {
1077 fsl,pins =
1078 <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */
1079 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */
1080 };
1081
1082 pinctrl_i2c3_gpio: i2c3gpiogrp {
1083 fsl,pins =
1084 <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */
1085 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */
1086 };
1087
1088 /* Verdin I2C_1 */
1089 pinctrl_i2c4: i2c4grp {
1090 fsl,pins =
1091 <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */
1092 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */
1093 };
1094
1095 pinctrl_i2c4_gpio: i2c4gpiogrp {
1096 fsl,pins =
1097 <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */
1098 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
1099 };
1100
1101 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1102 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1103 fsl,pins =
1104 <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */
1105 };
1106
1107 /* Verdin I2S_2_D_OUT shared with SAI3 */
1108 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1109 fsl,pins =
1110 <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */
1111 };
1112
1113 pinctrl_pcie: pciegrp {
1114 fsl,pins =
1115 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */
1116 <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */
1117 };
1118
1119 pinctrl_pmic: pmicirqgrp {
1120 fsl,pins =
1121 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */
1122 };
1123
1124 pinctrl_pwm_1: pwm1grp {
1125 fsl,pins =
1126 <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */
1127 };
1128
1129 pinctrl_pwm_2: pwm2grp {
1130 fsl,pins =
1131 <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */
1132 };
1133
1134 /* Verdin PWM_3_DSI shared with GPIO3_IO20 */
1135 pinctrl_pwm_3: pwm3grp {
1136 fsl,pins =
1137 <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */
1138 };
1139
1140 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */
1141 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {
1142 fsl,pins =
1143 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */
1144 };
1145
1146 pinctrl_reg_eth: regethgrp {
1147 fsl,pins =
1148 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */
1149 };
1150
1151 pinctrl_sai1: sai1grp {
1152 fsl,pins =
1153 <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */
1154 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */
1155 <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */
1156 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */
1157 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */
1158 };
1159
1160 pinctrl_sai3: sai3grp {
1161 fsl,pins =
1162 <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */
1163 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */
1164 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */
1165 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */
1166 };
1167
1168 pinctrl_uart1: uart1grp {
1169 fsl,pins =
1170 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */
1171 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */
1172 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */
1173 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */
1174 };
1175
1176 pinctrl_uart2: uart2grp {
1177 fsl,pins =
1178 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */
1179 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */
1180 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */
1181 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */
1182 };
1183
1184 pinctrl_uart3: uart3grp {
1185 fsl,pins =
1186 <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */
1187 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */
1188 };
1189
1190 /* Non-wifi usage only */
1191 pinctrl_uart4: uart4grp {
1192 fsl,pins =
1193 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */
1194 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */
1195 };
1196
1197 pinctrl_usb1_vbus: usb1vbusgrp {
1198 fsl,pins =
1199 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x19>; /* SODIMM 155 */
1200 };
1201
1202 /* USB_1_ID */
1203 pinctrl_usb_1_id: usb1idgrp {
1204 fsl,pins =
1205 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */
1206 };
1207
1208 pinctrl_usb2_vbus: usb2vbusgrp {
1209 fsl,pins =
1210 <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19>; /* SODIMM 185 */
1211 };
1212
1213 /* On-module Wi-Fi */
1214 pinctrl_usdhc1: usdhc1grp {
1215 fsl,pins =
1216 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>,
1217 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>,
1218 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>,
1219 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>,
1220 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>,
1221 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>;
1222 };
1223
1224 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1225 fsl,pins =
1226 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>,
1227 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>,
1228 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>,
1229 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>,
1230 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>,
1231 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>;
1232 };
1233
1234 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1235 fsl,pins =
1236 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>,
1237 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>,
1238 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>,
1239 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>,
1240 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>,
1241 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>;
1242 };
1243
1244 pinctrl_usdhc2_cd: usdhc2cdgrp {
1245 fsl,pins =
1246 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */
1247 };
1248
1249 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1250 fsl,pins =
1251 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */
1252 };
1253
1254 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1255 fsl,pins =
1256 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */
1257 };
1258
1259 pinctrl_usdhc2: usdhc2grp {
1260 fsl,pins =
1261 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */
1262 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */
1263 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */
1264 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */
1265 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */
1266 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */
1267 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */
1268 };
1269
1270 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1271 fsl,pins =
1272 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1273 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
1274 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
1275 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
1276 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
1277 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
1278 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
1279 };
1280
1281 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1282 fsl,pins =
1283 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1284 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>,
1285 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>,
1286 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>,
1287 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>,
1288 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>,
1289 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>;
1290 };
1291
1292 /* Avoid backfeeding with removed card power */
1293 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1294 fsl,pins =
1295 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>,
1296 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>,
1297 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>,
1298 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>,
1299 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>,
1300 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>,
1301 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>;
1302 };
1303
1304 pinctrl_usdhc3: usdhc3grp {
1305 fsl,pins =
1306 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1307 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>,
1308 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>,
1309 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>,
1310 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>,
1311 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>,
1312 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>,
1313 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>,
1314 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>,
1315 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>,
1316 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>,
1317 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>;
1318 };
1319
1320 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1321 fsl,pins =
1322 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1323 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>,
1324 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
1325 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
1326 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
1327 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
1328 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
1329 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
1330 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
1331 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
1332 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
1333 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>;
1334 };
1335
1336 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1337 fsl,pins =
1338 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1339 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>,
1340 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>,
1341 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>,
1342 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>,
1343 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>,
1344 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>,
1345 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>,
1346 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>,
1347 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>,
1348 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>,
1349 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>;
1350 };
1351
1352 pinctrl_wdog: wdoggrp {
1353 fsl,pins =
1354 <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */
1355 };
1356
1357 pinctrl_bluetooth_ctrl: bluetoothctrlgrp {
1358 fsl,pins =
1359 <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */
1360 };
1361
1362 pinctrl_wifi_ctrl: wifictrlgrp {
1363 fsl,pins =
1364 <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */
1365 };
1366
1367 pinctrl_wifi_i2s: wifii2sgrp {
1368 fsl,pins =
1369 <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */
1370 <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */
1371 <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */
1372 <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */
1373 };
1374
1375 pinctrl_wifi_pwr_en: wifipwrengrp {
1376 fsl,pins =
1377 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */
1378 };
1379};