Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 331f7f98b10190fa72dd8d40b91eb725e9484a93 / . / configs / ls2081ardb_defconfig
blob: 2a8a562f60e2174138bb31ab3fe2e0a23ca23237 [file] [log] [blame]
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]1CONFIG_ARM=y
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]2CONFIG_GIC_V3_ITS=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]3CONFIG_TARGET_LS2081ARDB=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]4CONFIG_SYS_TEXT_BASE=0x20100000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]5CONFIG_SYS_MALLOC_LEN=0x202000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]6CONFIG_NR_DRAM_BANKS=3
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]7CONFIG_ENV_SIZE=0x2000
8CONFIG_ENV_OFFSET=0x300000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]9CONFIG_ENV_SECT_SIZE=0x40000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]10CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb"
Tom Rini2c082ab2021-07-26 21:10:37 -0400[diff] [blame]11CONFIG_FSL_USE_PCA9547_MUX=y
Tom Rini89cdcab2021-12-12 22:12:31 -0500[diff] [blame]12CONFIG_VID=y
13CONFIG_VID_FLS_ENV="ls2080ardb_vdd_mv"
14CONFIG_VOL_MONITOR_IR36021_READ=y
15CONFIG_VOL_MONITOR_IR36021_SET=y
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]16CONFIG_FSL_LS_PPA=y
17CONFIG_QSPI_AHB_INIT=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]18CONFIG_AHCI=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]19# CONFIG_SYS_MALLOC_F is not set
Alper Nebi Yasak2beb0f42022-01-29 18:25:30 +0300[diff] [blame]20CONFIG_REMAKE_ELF=y
Tom Rini5ca768d2022-01-24 21:08:41 +0000[diff] [blame]21CONFIG_MP=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]22CONFIG_FIT_VERBOSE=y
23CONFIG_OF_BOARD_SETUP=y
24CONFIG_OF_STDOUT_VIA_ALIAS=y
Tom Rini8c70baa2021-12-14 13:36:40 -0500[diff] [blame]25CONFIG_DYNAMIC_SYS_CLK_FREQ=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]26CONFIG_QSPI_BOOT=y
27CONFIG_BOOTDELAY=10
Sam Protsenkobd7bffe2017-08-14 20:22:17 +0300[diff] [blame]28CONFIG_USE_BOOTARGS=y
29CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]30CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;"
Adam Ford10541762018-07-29 13:13:29 -0500[diff] [blame]31CONFIG_MISC_INIT_R=y
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]32CONFIG_CMD_GREPENV=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]33CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]34CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]35CONFIG_CMD_I2C=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]36CONFIG_CMD_MMC=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]37CONFIG_CMD_PCI=y
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]38CONFIG_CMD_USB=y
39# CONFIG_CMD_SETEXPR is not set
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]40CONFIG_CMD_CACHE=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]41CONFIG_OF_CONTROL=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]42CONFIG_ENV_OVERWRITE=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]43CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]44CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]45CONFIG_NET_RANDOM_ETHADDR=y
46CONFIG_DM=y
Simon Glass701ef062022-01-31 07:49:33 -0700[diff] [blame]47CONFIG_SATA=y
Tom Rinif4e64b92022-02-08 23:50:55 +0000[diff] [blame]48CONFIG_SCSI_AHCI=y
Peng Ma1c4bf2f2019-01-30 19:17:44 +0800[diff] [blame]49CONFIG_SATA_CEVA=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]50CONFIG_FSL_CAAM=y
Tom Rinif7246c22021-08-21 13:50:17 -0400[diff] [blame]51CONFIG_DDR_CLK_FREQ=133333333
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]52CONFIG_DDR_ECC=y
53CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
Tom Rini52b2e262021-08-18 23:12:24 -0400[diff] [blame]54CONFIG_SYS_I2C_LEGACY=y
Tom Rini714482a2021-08-18 23:12:25 -0400[diff] [blame]55CONFIG_SYS_I2C_EARLY_INIT=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]56CONFIG_SYS_I2C_EEPROM_ADDR=0x57
Mario Six41d7d972018-03-28 14:38:19 +0200[diff] [blame]57CONFIG_FSL_ESDHC=y
Miquel Raynal803baa22019-10-03 19:50:08 +0200[diff] [blame]58CONFIG_MTD=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]59CONFIG_DM_SPI_FLASH=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]60CONFIG_SPI_FLASH_STMICRO=y
Alexandru Gagniucd83e98c2017-08-01 17:19:59 -0700[diff] [blame]61CONFIG_PHYLIB=y
Jeremy Gebbenabe3edf2018-09-18 15:49:35 -0600[diff] [blame]62CONFIG_PHY_AQUANTIA=y
Tom Rini84e35db2019-11-26 17:32:42 -0500[diff] [blame]63CONFIG_PHY_CORTINA=y
Kuldeep Singh016965f2021-08-10 11:20:07 +0530[diff] [blame]64CONFIG_CORTINA_FW_ADDR=0x980000
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]65CONFIG_E1000=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]66CONFIG_MII=y
Tom Rinifa943162020-10-29 10:48:01 -0400[diff] [blame]67CONFIG_NVME=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]68CONFIG_PCI=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]69CONFIG_DM_PCI_COMPAT=y
Hou Zhiqiang02f1f062020-07-09 23:31:42 +0800[diff] [blame]70CONFIG_PCIE_LAYERSCAPE_RC=y
Heiko Schocherb1f9d2c2020-10-16 10:41:46 +0200[diff] [blame]71CONFIG_RTC_PCF8563=y
Tom Rinie791a022017-08-11 11:20:19 -0400[diff] [blame]72CONFIG_SCSI=y
Peng Ma1c4bf2f2019-01-30 19:17:44 +0800[diff] [blame]73CONFIG_DM_SCSI=y
Tom Rinie69ba982018-03-06 19:02:27 -0500[diff] [blame]74CONFIG_CONS_INDEX=2
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]75CONFIG_SYS_NS16550=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]76CONFIG_SPI=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]77CONFIG_DM_SPI=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]78CONFIG_FSL_DSPI=y
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]79CONFIG_FSL_QSPI=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]80CONFIG_USB=y
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]81CONFIG_USB_XHCI_HCD=y
82CONFIG_USB_XHCI_DWC3=y