blob: 95e99eabd718ece927125c0ac78c1b7dab20189c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
York Sun7b08d212014-06-23 15:15:56 -07002/*
3 * Copyright 2014 Freescale Semiconductor
York Sun7b08d212014-06-23 15:15:56 -07004 */
5#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -06006#include <init.h>
York Sun7b08d212014-06-23 15:15:56 -07007#include <malloc.h>
8#include <errno.h>
Simon Glass0c364412019-12-28 10:44:48 -07009#include <net.h>
York Sun7b08d212014-06-23 15:15:56 -070010#include <netdev.h>
11#include <fsl_ifc.h>
12#include <fsl_ddr.h>
13#include <asm/io.h>
14#include <fdt_support.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090015#include <linux/libfdt.h>
J. German Rivera43e4ae32015-01-06 13:19:02 -080016#include <fsl-mc/fsl_mc.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060017#include <env_internal.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080018#include <asm/arch/soc.h>
York Sun7b08d212014-06-23 15:15:56 -070019
20DECLARE_GLOBAL_DATA_PTR;
21
22int board_init(void)
23{
24 init_final_memctl_regs();
Prabhakar Kushwahacf329182014-07-14 17:15:44 +053025
26#ifdef CONFIG_ENV_IS_NOWHERE
27 gd->env_addr = (ulong)&default_environment[0];
28#endif
29
York Sun7b08d212014-06-23 15:15:56 -070030 return 0;
31}
32
33int board_early_init_f(void)
34{
Scott Woodf64c98c2015-03-20 19:28:12 -070035 fsl_lsch3_early_init_f();
York Sun7b08d212014-06-23 15:15:56 -070036 return 0;
37}
38
York Sunc7a0e302014-08-13 10:21:05 -070039void detail_board_ddr_info(void)
40{
41 puts("\nDDR ");
42 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
43 print_ddr_info(0);
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053044#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Suncbe8e1c2016-04-04 11:41:26 -070045 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
York Sunc7a0e302014-08-13 10:21:05 -070046 puts("\nDP-DDR ");
47 print_size(gd->bd->bi_dram[2].size, "");
48 print_ddr_info(CONFIG_DP_DDR_CTRL);
49 }
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053050#endif
York Sunc7a0e302014-08-13 10:21:05 -070051}
52
York Sun7b08d212014-06-23 15:15:56 -070053int board_eth_init(bd_t *bis)
54{
55 int error = 0;
56
57#ifdef CONFIG_SMC91111
58 error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
59#endif
60
Santan Kumar1afa9002017-05-05 15:42:29 +053061#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
York Sun7b08d212014-06-23 15:15:56 -070062 error = cpu_eth_init(bis);
63#endif
64 return error;
65}
66
Santan Kumar1afa9002017-05-05 15:42:29 +053067#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
York Sun7b08d212014-06-23 15:15:56 -070068void fdt_fixup_board_enet(void *fdt)
69{
70 int offset;
71
Stuart Yodera3466152016-03-02 16:37:13 -060072 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
J. German Rivera43e4ae32015-01-06 13:19:02 -080073
74 /*
75 * TODO: Remove this when backward compatibility
Stuart Yodera3466152016-03-02 16:37:13 -060076 * with old DT node (/fsl-mc) is no longer needed.
J. German Rivera43e4ae32015-01-06 13:19:02 -080077 */
78 if (offset < 0)
Stuart Yodera3466152016-03-02 16:37:13 -060079 offset = fdt_path_offset(fdt, "/fsl-mc");
J. German Rivera43e4ae32015-01-06 13:19:02 -080080
81 if (offset < 0) {
82 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
83 __func__, offset);
84 return;
85 }
86
Mian Yousaf Kaukab97124652018-12-18 14:01:17 +010087 if (get_mc_boot_status() == 0 &&
88 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
York Sun7b08d212014-06-23 15:15:56 -070089 fdt_status_okay(fdt, offset);
90 else
91 fdt_status_fail(fdt, offset);
92}
Alexander Graf2ebeb442016-11-17 01:02:57 +010093
94void board_quiesce_devices(void)
95{
96 fsl_mc_ldpaa_exit(gd->bd);
97}
York Sun7b08d212014-06-23 15:15:56 -070098#endif
99
100#ifdef CONFIG_OF_BOARD_SETUP
Simon Glass2aec3cc2014-10-23 18:58:47 -0600101int ft_board_setup(void *blob, bd_t *bd)
York Sun7b08d212014-06-23 15:15:56 -0700102{
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530103 u64 base[CONFIG_NR_DRAM_BANKS];
104 u64 size[CONFIG_NR_DRAM_BANKS];
York Sun7b08d212014-06-23 15:15:56 -0700105
York Sun290a83a2014-09-08 12:20:01 -0700106 ft_cpu_setup(blob, bd);
107
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530108 /* fixup DT for the two GPP DDR banks */
109 base[0] = gd->bd->bi_dram[0].start;
110 size[0] = gd->bd->bi_dram[0].size;
111 base[1] = gd->bd->bi_dram[1].start;
112 size[1] = gd->bd->bi_dram[1].size;
113
York Sun4de24ef2017-03-06 09:02:28 -0800114#ifdef CONFIG_RESV_RAM
115 /* reduce size if reserved memory is within this bank */
116 if (gd->arch.resv_ram >= base[0] &&
117 gd->arch.resv_ram < base[0] + size[0])
118 size[0] = gd->arch.resv_ram - base[0];
119 else if (gd->arch.resv_ram >= base[1] &&
120 gd->arch.resv_ram < base[1] + size[1])
121 size[1] = gd->arch.resv_ram - base[1];
122#endif
123
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530124 fdt_fixup_memory_banks(blob, base, size, 2);
York Sun7b08d212014-06-23 15:15:56 -0700125
Nipun Guptad6912642018-08-20 16:01:14 +0530126 fdt_fsl_mc_fixup_iommu_map_entry(blob);
127
Santan Kumar1afa9002017-05-05 15:42:29 +0530128#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
York Sun7b08d212014-06-23 15:15:56 -0700129 fdt_fixup_board_enet(blob);
130#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -0600131
132 return 0;
York Sun7b08d212014-06-23 15:15:56 -0700133}
134#endif
Bogdan Purcareata08bc0142017-05-24 16:40:21 +0000135
136#if defined(CONFIG_RESET_PHY_R)
137void reset_phy(void)
138{
139}
140#endif
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000141
142#ifdef CONFIG_TFABOOT
143void *env_sf_get_env_addr(void)
144{
145 return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET);
146}
147#endif