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git01.mediatek.com / filogic / uboot / f6de3c549a677ba4d1d30ef9a506db9b329b50bd / . / include / configs / bf526-ezbrd.h
blob: 35a2228a6b871f2083196b6b8718b4786bb78435 [file] [log] [blame]
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]1/*
2 * U-boot - Configuration file for BF526 EZBrd board
3 */
4
5#ifndef __CONFIG_BF526_EZBRD_H__
6#define __CONFIG_BF526_EZBRD_H__
7
Mike Frysinger18a407c2009-04-24 17:22:40 -0400[diff] [blame]8#include <asm/config-pre.h>
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]9
10
11/*
12 * Processor Settings
13 */
Mike Frysinger5b0c1282010-12-23 14:58:37 -0500[diff] [blame]14#define CONFIG_BFIN_CPU bf526-0.0
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 16
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 5
40
41
42/*
43 * Memory Settings
44 */
45/* This board has a 64meg MT48H32M16 */
46#define CONFIG_MEM_ADD_WDTH 10
47#define CONFIG_MEM_SIZE 64
48
49#define CONFIG_EBIU_SDRRC_VAL 0x0267
50#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_4 | TRCD_2 | TWR_2 | PSS)
51
52#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
53#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
54#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
55
Mike Frysinger8fe89c12010-09-21 19:47:27 -0400[diff] [blame]56#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]57#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
58
59
60/*
61 * NAND Settings
62 * (can't be used same time as ethernet)
63 */
64#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
Mike Frysinger8fe89c12010-09-21 19:47:27 -0400[diff] [blame]65# define CONFIG_BFIN_NFC
66# define CONFIG_BFIN_NFC_BOOTROM_ECC
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]67#endif
68#ifdef CONFIG_BFIN_NFC
69#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
70#define CONFIG_DRIVER_NAND_BFIN
71#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
72#define CONFIG_SYS_MAX_NAND_DEVICE 1
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]73#define CONFIG_CMD_NAND
74#endif
75
76
77/*
78 * Network Settings
79 */
80#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
81 !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
82#define ADI_CMDS_NETWORK 1
83#define CONFIG_BFIN_MAC
84#define CONFIG_RMII
85#define CONFIG_NETCONSOLE 1
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]86#endif
87#define CONFIG_HOSTNAME bf526-ezbrd
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]88
89/*
90 * Flash Settings
91 */
92#define CONFIG_FLASH_CFI_DRIVER
93#define CONFIG_SYS_FLASH_BASE 0x20000000
94#define CONFIG_SYS_FLASH_CFI
95#define CONFIG_SYS_FLASH_PROTECTION
96#define CONFIG_SYS_MAX_FLASH_BANKS 1
97#define CONFIG_SYS_MAX_FLASH_SECT 71
98
99
100/*
101 * SPI Settings
102 */
103#define CONFIG_BFIN_SPI
104#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysinger9a4406462009-06-14 22:29:35 -0400[diff] [blame]105#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]106
107
108/*
109 * Env Storage Settings
110 */
111#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
112#define CONFIG_ENV_IS_IN_SPI_FLASH
113#define CONFIG_ENV_OFFSET 0x4000
114#define CONFIG_ENV_SIZE 0x2000
115#define CONFIG_ENV_SECT_SIZE 0x2000
116#else
117#define CONFIG_ENV_IS_IN_FLASH
118#define CONFIG_ENV_OFFSET 0x4000
119#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
120#define CONFIG_ENV_SIZE 0x2000
121#define CONFIG_ENV_SECT_SIZE 0x2000
122#endif
Mike Frysinger45b57bd2009-07-21 22:17:36 -0400[diff] [blame]123#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]124
125
126/*
127 * I2C Settings
128 */
Scott Jiang80d27fa2014-11-13 15:30:55 +0800[diff] [blame]129#define CONFIG_SYS_I2C
Scott Jiang655761e2014-11-13 15:30:53 +0800[diff] [blame]130#define CONFIG_SYS_I2C_ADI
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]131
132
133/*
134 * USB Settings
135 */
136#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
137#define CONFIG_USB
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +0200[diff] [blame]138#define CONFIG_USB_MUSB_HCD
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]139#define CONFIG_USB_BLACKFIN
140#define CONFIG_USB_STORAGE
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +0200[diff] [blame]141#define CONFIG_USB_MUSB_TIMEOUT 100000
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]142#endif
143
144
145/*
146 * Misc Settings
147 */
148#define CONFIG_MISC_INIT_R
149#define CONFIG_RTC_BFIN
150#define CONFIG_UART_CONSOLE 1
151
152/* define to enable run status via led */
153/* #define CONFIG_STATUS_LED */
154#ifdef CONFIG_STATUS_LED
Mike Frysinger074d0422010-06-02 05:12:11 -0400[diff] [blame]155#define CONFIG_GPIO_LED
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]156#define CONFIG_BOARD_SPECIFIC_LED
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]157/* use LED0 to indicate booting/alive */
158#define STATUS_LED_BOOT 0
Mike Frysinger074d0422010-06-02 05:12:11 -0400[diff] [blame]159#define STATUS_LED_BIT GPIO_PF8
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]160#define STATUS_LED_STATE STATUS_LED_ON
161#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
162/* use LED1 to indicate crash */
163#define STATUS_LED_CRASH 1
Mike Frysinger074d0422010-06-02 05:12:11 -0400[diff] [blame]164#define STATUS_LED_BIT1 GPIO_PG11
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]165#define STATUS_LED_STATE1 STATUS_LED_ON
166#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
Mike Frysinger074d0422010-06-02 05:12:11 -0400[diff] [blame]167/* #define STATUS_LED_BIT2 GPIO_PG12 */
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]168#endif
169
170
171/*
172 * Pull in common ADI header for remaining command/environment setup
173 */
174#include <configs/bfin_adi_common.h>
175
Mike Frysinger03783552008-10-12 21:30:48 -0400[diff] [blame]176#endif