blob: c49d3062954f109daa541bcfaadc59fe37c8f287 [file] [log] [blame]
Stelian Popd1aea1c2008-01-30 21:15:54 +00001/*
2 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Popd1aea1c2008-01-30 21:15:54 +00004 * Lead Tech Design <www.leadtechdesign.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Stelian Popd1aea1c2008-01-30 21:15:54 +00007 */
8
9#include <common.h>
Reinhard Meyerb06208c2010-11-07 13:26:14 +010010#include <asm/io.h>
Stelian Popd1aea1c2008-01-30 21:15:54 +000011#include <asm/arch/hardware.h>
Stelian Popd4bfbc52008-03-26 20:52:32 +010012#include <asm/arch/at91_pit.h>
Jean-Christophe PLAGNIOL-VILLARD1d4a3792009-04-16 21:30:48 +020013#include <asm/arch/clk.h>
Jean-Christophe PLAGNIOL-VILLARD1d4a3792009-04-16 21:30:48 +020014#include <div64.h>
Stelian Popd1aea1c2008-01-30 21:15:54 +000015
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020016#if !defined(CONFIG_AT91FAMILY)
17# error You need to define CONFIG_AT91FAMILY in your board config!
18#endif
19
20DECLARE_GLOBAL_DATA_PTR;
21
Stelian Popd1aea1c2008-01-30 21:15:54 +000022/*
Stelian Popeea44aa2008-03-26 20:52:28 +010023 * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
Stelian Popd1aea1c2008-01-30 21:15:54 +000024 * setting the 20 bit counter period to its maximum (0xfffff).
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020025 * (See the relevant data sheets to understand that this really works)
26 *
27 * We do also mimic the typical powerpc way of incrementing
28 * two 32 bit registers called tbl and tbu.
29 *
30 * Those registers increment at 1/16 the main clock rate.
Stelian Popd1aea1c2008-01-30 21:15:54 +000031 */
Stelian Popd1aea1c2008-01-30 21:15:54 +000032
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020033#define TIMER_LOAD_VAL 0xfffff
Jean-Christophe PLAGNIOL-VILLARD1d4a3792009-04-16 21:30:48 +020034
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020035/*
36 * Use the PITC in full 32 bit incrementing mode
37 */
Stelian Pop6bf2de22008-03-26 21:52:27 +010038int timer_init(void)
Stelian Popd1aea1c2008-01-30 21:15:54 +000039{
Reinhard Meyere260d0b2010-11-03 15:39:55 +010040 at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020041
Wenyou Yang57b7f292016-02-03 10:16:49 +080042 at91_periph_clk_enable(ATMEL_ID_SYS);
Stelian Popd1aea1c2008-01-30 21:15:54 +000043
44 /* Enable PITC */
Jens Scharsiga4db1ca2010-02-03 22:46:58 +010045 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
Stelian Popd1aea1c2008-01-30 21:15:54 +000046
Simon Glass6ed6e032012-12-13 20:48:32 +000047 gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
Jean-Christophe PLAGNIOL-VILLARD1d4a3792009-04-16 21:30:48 +020048
Stelian Popd1aea1c2008-01-30 21:15:54 +000049 return 0;
50}
51
52/*
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020053 * Return the number of timer ticks per second.
Stelian Popd1aea1c2008-01-30 21:15:54 +000054 */
55ulong get_tbclk(void)
56{
Simon Glass6ed6e032012-12-13 20:48:32 +000057 return gd->arch.timer_rate_hz;
Stelian Popd1aea1c2008-01-30 21:15:54 +000058}