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git01.mediatek.com / filogic / uboot / f6aa39e58128a81a46b0d3a909ace31f9e767632 / . / arch / arm / lib / bootm-fdt.c
blob: 4481f9e2fa9ceb26f2f54f21e67f6b825c016601 [file] [log] [blame]
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]1/*
2 * Copyright (c) 2013, Google Inc.
3 *
4 * Copyright (C) 2011
5 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
6 * - Added prep subcommand support
7 * - Reorganized source - modeled after powerpc version
8 *
9 * (C) Copyright 2002
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Marius Groeger <mgroeger@sysgo.de>
12 *
13 * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
14 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]15 * SPDX-License-Identifier: GPL-2.0+
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]16 */
17
18#include <common.h>
19#include <fdt_support.h>
Tom Rini9fcb5ef2015-05-14 11:07:03 -0400[diff] [blame]20#ifdef CONFIG_ARMV7_NONSEC
Jan Kiszkacb334402015-04-21 07:18:32 +0200[diff] [blame]21#include <asm/armv7.h>
Tom Rini9fcb5ef2015-05-14 11:07:03 -0400[diff] [blame]22#endif
Tom Rinifb02cc12015-03-05 20:19:36 -0500[diff] [blame]23#include <asm/psci.h>
Masahiro Yamada2663cd62016-06-27 19:31:05 +0900[diff] [blame]24#include <asm/spin_table.h>
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]25
26DECLARE_GLOBAL_DATA_PTR;
27
Ma Haijun62358242014-07-12 14:24:06 +0100[diff] [blame]28int arch_fixup_fdt(void *blob)
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]29{
30 bd_t *bd = gd->bd;
Marc Zyngierb32cf0e2014-07-12 14:24:07 +0100[diff] [blame]31 int bank, ret;
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]32 u64 start[CONFIG_NR_DRAM_BANKS];
33 u64 size[CONFIG_NR_DRAM_BANKS];
34
35 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
36 start[bank] = bd->bi_dram[bank].start;
37 size[bank] = bd->bi_dram[bank].size;
Jan Kiszkacb334402015-04-21 07:18:32 +0200[diff] [blame]38#ifdef CONFIG_ARMV7_NONSEC
39 ret = armv7_apply_memory_carveout(&start[bank], &size[bank]);
40 if (ret)
41 return ret;
42#endif
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]43 }
44
Marc Zyngierb32cf0e2014-07-12 14:24:07 +0100[diff] [blame]45 ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
Marc Zyngierb32cf0e2014-07-12 14:24:07 +0100[diff] [blame]46 if (ret)
47 return ret;
48
Masahiro Yamada2663cd62016-06-27 19:31:05 +0900[diff] [blame]49#ifdef CONFIG_ARMV8_SPIN_TABLE
50 ret = spin_table_update_dt(blob);
51 if (ret)
52 return ret;
53#endif
54
Hou Zhiqiangdae02772016-06-28 20:18:16 +0800[diff] [blame]55#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI)
Tom Rinifb02cc12015-03-05 20:19:36 -0500[diff] [blame]56 ret = psci_update_dt(blob);
Masahiro Yamada909cc1c2016-06-17 21:51:48 +0900[diff] [blame]57 if (ret)
58 return ret;
Marc Zyngierb32cf0e2014-07-12 14:24:07 +0100[diff] [blame]59#endif
Masahiro Yamada909cc1c2016-06-17 21:51:48 +0900[diff] [blame]60
61 return 0;
Simon Glass653909f2013-05-08 08:06:03 +0000[diff] [blame]62}